View STM32F756NG_8173937.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

for further information contact your local stmicroelectronics sales office. november 2014 docid026379 rev 2 1/108 stm32f756xx arm ? -based cortex ? -m7 32b mcu+fpu, 428dmips, up to 1mb flash/320+16+ 4kb ram, crypto, usb otg hs/fs, ethernet, 18 tims, 3 adcs, 25 com itf, cam & lcd data brief features ? core: arm ? 32-bit cortex ? -m7 cpu with fpu, adaptive real-time accelerator (art accelerator?) and l1 cache: 4kb data cache and 4kb instruction ca che, allowing 0-wait state execution from embedded flash memory and external memories, frequency up to 200 mhz, mpu, 428 dmips/2.14 dmips/mhz (dhrystone 2.1), and dsp instructions. ? memories ? up to 1mb of flash memory ? sram: 320kb (including 64kb of data tcm ram for critical real time data) + 16kb of instruction tcm ram (for critical real time routines) + 4kb of backup sram (available in the lowest power modes) ? flexible external memory controller with up to 32-bit data bus: sram, psram, sdram/lpsdr sdram, nor/nand memories ? dual mode quad spi ? lcd parallel interface, 8080/6800 modes ? lcd-tft controller up to xga resolution with dedicated chrom-art accelerator? for enhanced graphic content creation (dma2d) ? clock, reset and supply management ? 1.7 v to 3.6 v application supply and i/os ? por, pdr, pvd and bor ? dedicated usb power ? 4-to-26 mhz crystal oscillator ? internal 16 mhz factory-trimmed rc (1% accuracy) ? 32 khz oscillator for rtc with calibration ? internal 32 khz rc with calibration ? low power ? sleep, stop and standby modes ?v bat supply for rtc, 3232 bit backup registers + 4kb backup sram ? 312-bit, 2.4 msps adc: up to 24 channels and 7.2 msps in trip le interleaved mode ? 212-bit d/a converters ? general-purpose dma: 16-stream dma controller with fifos and burst support ? up to 18 timers: up to thirteen 16-bit (1x low power 16-bit timer available in stop mode) and two 32-bit timers, each with up to 4 ic/oc/pwm or pulse counter and quadrature (incremental) encoder input. all 15 timers running up to 200 mhz. 2x watchdogs, systick timer ? debug mode ? swd & jtag interfaces ?cortex ? -m7 trace macrocell? ? up to 168 i/o ports with interrupt capability ? up to 164 fast i/os up to 100 mhz ? up to 166 5 v-tolerant i/os ? up to 25 communica tion interfaces ? up to 4 i 2 c interfaces (smbus/pmbus) ? up to 4 usarts/4 uarts (12.5 mbit/s, iso7816 interface, lin, irda, modem control) ? up to 6 spis (up to 50 mbits/s), 3 with muxed simplex i 2 s for audio class accuracy via internal audio pll or external clock ? 2 x sai (serial audio interface) ? 2 can (2.0b active) and sdmmc interface ? spdif-in interface ? hdmi-cec ? advanced connectivity ? usb 2.0 full-speed device/host/otg controller with on-chip phy ? usb 2.0 high-speed/full-speed device/host/otg controller with dedicated dma, on-chip full-speed phy and ulpi ? 10/100 ethernet mac with dedicated dma: supports ieee 1588v2 hardware, mii/rmii ? 8- to 14-bit parallel camera interface up to 54 mbytes/s ? cryptographic acceleration: hardware acceleration for aes 128, 192, 256, triple des, hash (md5, sha- 1, sha-2), and hmac ? true random number generator ? crc calculation unit ? rtc: subsecond accuracy, hardware calendar ? 96-bit unique id table 1. device summary reference part number stm32f756xx stm32f756vg, stm32f756zg, stm32f756ig, stm32f756bg, STM32F756NG, stm32f756ie, stm32f756ve, stm32f756ze, stm32f756be, stm32f756ne lqfp100 (14 14 mm) lqfp144 (20 20 mm) lqfp176 (24 24 mm) ufbga176 (10 x 10 mm) &"'! tfbga216 (13 x 13 mm) lqfp208 (28 x 28 mm) wlcsp143 www.st.com
contents stm32f756xx 2/108 docid026379 rev 2 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 arm ? cortex ? -m7 with fpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2 memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4 crc (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 13 2.5 embedded sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.6 axi-ahb bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.7 dma controller (dma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.8 flexible memory controller (fmc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.9 quad spi memory interface (quadspi) . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.10 lcd-tft controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.11 chrom-art accelerator? (dma2d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.12 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . . 17 2.13 external interrupt/event controller (exti) . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.14 clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.15 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.16 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.17 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.17.1 internal reset on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.17.2 internal reset off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.18 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.18.1 regulator on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.18.2 regulator off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.18.3 regulator on/off and inte rnal reset on/off availability . . . . . . . . . . 24 2.19 real-time clock (rtc), backup sram and backup registers . . . . . . . . . . 24 2.20 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.21 v bat operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.22 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.22.1 advanced-control timers (tim1, tim8) . . . . . . . . . . . . . . . . . . . . . . . . . 27
docid026379 rev 2 3/108 stm32f756xx contents 4 2.22.2 general-purpose timers (timx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.22.3 basic timers tim6 and tim7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.22.4 low-power timer (lptim1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.22.5 independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.22.6 window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.22.7 systick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.23 inter-integrated circuit interface (i 2 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.24 universal synchronous/asynchronous re ceiver transmitters (usart) . . 30 2.25 serial peripheral interface (spi)/inter- integrated sound interfaces (i2s) . 32 2.26 serial audio interface (sai) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.27 spdif-rx receiver interface (spdif-rx) . . . . . . . . . . . . . . . . . . . . . . . 32 2.28 audio pll (plli2s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.29 audio and lcd pll(pllsai) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.30 sd/sdio/mmc card host interface (sdmmc) . . . . . . . . . . . . . . . . . . . . . 33 2.31 ethernet mac interface with dedi cated dma and ieee 1588 support . . . 34 2.32 controller area network (bxcan) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.33 universal serial bus on-the-go full-speed (otg_fs) . . . . . . . . . . . . . . . . 35 2.34 universal serial bus on-the-go high-speed (otg_hs) . . . . . . . . . . . . . . . 35 2.35 high-definition multimedia interface (hdmi) - consumer electronics control (cec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.36 digital camera interface (dcmi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.37 cryptographic acceleration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.38 random number generator (rng) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.39 general-purpose input/outputs (gpios) . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.40 analog-to-digital converters (adcs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.41 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.42 digital-to-analog converter (dac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.43 serial wire jtag debug port (swj-dp) . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.44 embedded trace macrocell? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3 pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
contents stm32f756xx 4/108 docid026379 rev 2 5.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 6 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 appendix a recommendations when using inte rnal reset off . . . . . . . . . . . 106 a.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
docid026379 rev 2 5/108 stm32f756xx list of tables 5 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. stm32f756xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3. voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . . 21 table 4. regulator on/off and internal reset on/off availability. . . . . . . . . . . . . . . . . . . . . . . . . 24 table 5. voltage regulator modes in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 6. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 7. i2c implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 8. usart implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 9. legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 10. stm32f756xx pin and ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 11. fmc pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 12. stm32f756xx alternate function ma pping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 13. stm32f756xx register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 14. lqpf100, 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . . . 87 table 15. wlcsp143, 0.4 mm pitch wafer level chip scale package mechanical data . . . . . . . . . . . 90 table 16. lqfp144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 17. lqfp176, 24 x 24 mm, 176-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 18. lqfp208, 28 x 28 mm, 208-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 19. ufbga176+25 - ultra thin fine pitch ball grid array 10 10 0.6 mm mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 20. tfbga216 - thin fine pitch ball grid array 13 13 0.8mm package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 21. package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 22. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 23. limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 106 table 24. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
list of figures stm32f756xx 6/108 docid026379 rev 2 list of figures figure 1. compatible board design for lqfp100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 2. stm32f756xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 3. stm32f756xx axi-ahb bus matrix architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 4. power supply supervisor interconnection with in ternal reset off . . . . . . . . . . . . . . . . . . . 19 figure 5. pdr_on control with internal re set off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 6. regulator off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 7. startup in regulator off: slow v dd slope - power-down reset risen after v cap_1 /v cap_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 8. startup in regulator off mode: fast v dd slope - power-down reset risen before v cap_1 /v cap_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 23 figure 9. stm32f756xx lqfp100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 10. stm32f756xx wlcsp143 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 11. stm32f756xx lqfp144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1 figure 12. stm32f756xx lqfp176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 figure 13. stm32f756xx lqfp208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 figure 14. stm32f756xx ufbga176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 15. stm32f756xx tfbga216 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 16. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 17. lqfp100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 86 figure 18. lqpf100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8 figure 19. lqfp100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 20. wlcsp143, 0.4 mm pitch wafer level chip scale package outline . . . . . . . . . . . . . . . . . . . 89 figure 21. lqfp144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 91 figure 22. lqfp144 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 figure 23. lqfp144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 24. lqfp176 24 x 24 mm, 176-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 94 figure 25. lqfp176 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 figure 26. lqfp176 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 27. lqfp208, 28 x 28 mm, 208-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 98 figure 28. lqfp208 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 9 figure 29. ufbga176+25 - ultra thin fine pitch ball grid array 10 10 0.6 mm, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 30. ufbga176+25 marking example (package top view ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 figure 31. tfbga216 - thin fine pitch ball grid array 13 13 0.8mm, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 32. tfbga216 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
docid026379 rev 2 7/108 stm32f756xx description 38 1 description the stm32f756xx devices are based on the high-performance arm ? cortex ? -m7 32-bit risc core operating at up to 200 mhz frequency. the cortex ? -m7 core features a single floating point unit (sfpu) pr ecision which supports all arm ? single-precision data- processing instructions and data types. it also implements a full set of dsp instructions and a memory protection unit (mpu) which enhances application security. the stm32f756xx devices incorporate high-speed embedded memories with flash memory up to 1 mbyte, 320 kb of sram (including 64 kb of data tcm ram for critical real time data), 16 kb of instruction tcm ram (for cr itical real time routines), 4 kb of backup sram available in the lowest power modes, and an extensive range of enhanced i/os and peripherals connected to two apb buses, two ahb buses, a 32 -bit multi-ahb bus matrix and a multi layer axi interconnect supporting internal and external memories access. all devices offer three 12-bit adcs, two dacs, a low-power rtc, twelve general-purpose 16-bit timers including two pwm timers for mo tor control, two general-purpose 32-bit timers, a true random number generator (rng), and a cryptographic acceleration cell. they also feature standard and advanced communication interfaces. ? up to four i 2 cs ? six spis, three i 2 ss in duplex mode. to achieve audio class accuracy, the i 2 s peripherals can be clocked via a dedicated internal audio pll or via an external clock to allow synchronization. ? four usarts plus four uarts ? an usb otg full-spee d and a usb otg high- speed with full-speed capability (with the ulpi), ? two cans ? two sai serial audio interfaces ? an sdmmc host interface ? ethernet and camera interface ? lcd-tft display controller ? chrom-art accelerator?. ? spdif-rx interface ? hdmi-cec advanced peripherals include an sdmmc interf ace, a flexible memory control (fmc) interface, a quad spi flash memories interfac e, a camera interface for cmos sensors and a cryptographic accelera tion cell. refer to table 2: stm32f756xx features and peripheral counts for the list of peripherals available on each part number. the stm32f756xx devices operate in the ?40 to +105 c temperature range from a 1.7 to 3.6 v power supply. a dedicated supply input for usb (otg_fs and otg_hs) is available on all packages except lqfp100 fo r greater power supply choice. the supply voltage can drop to 1.7 v with the use of an external power supply supervisor (refer to section 2.17.2: internal reset off ). a comprehensive set of power-saving mode allows the design of low-power applications. the stm32f756xx devices offer devices in 7 packages ranging from 100 pins to 216 pins. the set of included peripherals changes with the device chosen.
description stm32f756xx 8/108 docid026379 rev 2 these features make the stm32f756xx microc ontrollers suitable for a wide range of applications: ? motor drive and application control ? medical equipment ? industrial applications: plc, inverters, circuit breakers ? printers, and scanners ? alarm systems, video intercom, and hvac ? home audio appliances ? mobile applications, internet of things ? wearable devices: smartwatches. figure 2 shows the general block diagram of the device family table 2. stm32f756xx features and peripheral counts peripherals stm32f756vx stm32f756zx stm32f756ix stm32f756bx stm32f756nx flash memory in kbytes 512 1024 512 1024 512 1024 512 1024 512 1024 sram in kbytes system 320(240+16+64) instruction 16 backup 4 fmc memory controller yes (1) ethernet yes timers general-purpose 10 advanced- control 2 basic 2 low-power 1 random number generator yes communication interfaces spi / i 2 s 4/3 (simplex) (2) 6/3 (simplex) (2) i 2 c4 usart/uart 4/4 usb otg fs yes usb otg hs yes can 2 sai 2 spdif-rx 4 inputs sdmmc yes camera interface yes lcd-tft yes chrom-art accelerator? (dma2d) yes cryptography yes gpios 82 114 140 168 12-bit adc number of channels 3 16 24
docid026379 rev 2 9/108 stm32f756xx description 38 12-bit dac number of channels yes 2 maximum cpu frequency 200 mhz operating voltage 1.7 to 3.6 v (3) operating temperatures ambient temperatures: ?40 to +85 c /?40 to +105 c junction temperature: ?40 to + 125 c package lqfp100 wlcsp143 lqfp144 ufbga176 lqfp176 lqfp208 tfbga216 1. for the lqfp100 package, only fmc bank1 is available. bank1 can only support a multiplexed nor/psram memory using the ne1 chi p select. 2. the spi1, spi2 and spi3 interfaces give the flexibility to work in an exclusive way in either the spi mode or the i2s audio m ode. 3. vdd/vdda minimum value of 1.7 v is obtained when the internal reset is off (refer to section 2.17.2: internal reset off ). table 2. stm32f756xx features and peripheral counts (continued) peripherals stm32f756vx stm32f756zx stm32f756ix stm32f756bx stm32f756nx
description stm32f756xx 10/108 docid026379 rev 2 1.1 full compatibility throughout the family the stm32f756xx devices are fully pin-to-pin, compatible with the stm32f4xx devices, allowing the user to try different peripherals, and reaching higher performances (higher frequency) for a greater degree of freedom during the development cycle. figure 1 give compatible board design s between the stm32f4xx families. figure 1. compatible board design for lqfp100 package the stm32f75x lqfp144, lqfp176, lqfp208, tfbga216, ufbga176, wlcsp143 packages are fully pin to pin co mpatible with stm32f4xx devices. 069 3& 9'' 966$ 95() 9''$ 3$ 966 9'' 3$ 3$ 3$ 3$ 3& 3% 3% 3% 3( 3( 3( 3( 3( 3( 3( 3( 3& 3% 3% 9&$3 9'' 3( 670)[[dqg670)[[olqhv 670)[[dqg670)[[olqhv 670)[[dqg670)[[olqhv 670)[[dqg670)[[olqhv 670)[[olqhv 966 9'' 966 3$ 3$ 3$ 3$ 3& 3% 3% 3% 3( 3( 3( 3( 3( 3( 3( 3( 3& 3% 3% 9&$3 9'' 3( 3& 966$ 95() 9''$ 3lqvwrduhqrwfrpsdwleoh 3$:.83 3$ 3$ 3$ 3$:.83 3$ 3$
docid026379 rev 2 11/108 stm32f756xx description 38 figure 2. stm32f756xx block diagram 1. the timers connected to apb2 are clocke d from timxclk up to 200 mhz, while the timers connected to apb1 are clocked from timxclk either up to 100 mhz or 200 mhz depending on timpre bit configuration in the rcc_dckcfgr register. 069 'w/kwkzd ,lw? yd/dxt<hw ?& w??w? d/dlwtd e}u?oxzvx~d/dz,?we?eu ezvx~d/dz,?we?dzu </e?& h^zd zyudyuu^u^d?& /??l^dh^ ?z?v?d l dl &/&k d//}?zd//?& d/k?& h^ kd',^ wud h>w/w??w?u^><?w?u^e?w?u ^etue> et/du/edz ze' u? ]v??( ,^zeus^ze wh/y>??l, de ' d zd z ,^ z >^ ^?v? ]v??( /t' ?s th z??? o}l }v??}o w>>u?u? w>^ d/de d/d? ?zvvo??& o zvvo? &>^,d d/d d/d d/d? d/d? d/de d/d? d/d? &/&k w?d,~u? ^zd?< ,??d, dl &/&k d ?^??u? &/&k w??w? w??w? w??w? w??w? w&??w? w'??w? w,??w? w/??w? 'w/kwkzd 'w/kwkzd 'w/kwkzd 'w/kwkzd 'w/kwkzd& 'w/kwkzd' 'w/kwkzd, 'w/kwkzd/ d/d?lwtd d/d d/d ?u? ]? h^zd e}u?oxzvx~d/d?z,?we?eu ezvx~d/d?z,?we?udzu </e?& zvvo?& zvvo?& zyudyuu^u^d?& ^>u^u^d?& ^w/?l/?^? dk^/l^u^^ k^z/e k^zkhd ,>k^ er?d, &/&k ^w/e ^rd&d &/&k ,zkdrzd ~d? w:??w? 'w/kwkzd: w<?& &/&k ez^ue^ues d^u^?? ,^, &/&k &/&k >zz?w?u>z'?w?u>z?w?u >z,^zeu>zs^zeu>zu >z>< zdz& zdz& zdz?, zd }???rd y/d ,w ,^ dd /dd dz< dz??w? :dz^du:d/u :d< :dkl^tu:dk :d'?^t es/ dd dwh ddzde< /ddzd< y^w/ >wd/d ,d/z?& ,d/r ^w/& ^w/&zzy??w??& ^>u^u^d?& /?el^dh^ ^/? ^u^<?& &/&k ???vouu}??}v??}oo?~&d ^zdu^zduw^zduekz&o?zu ee&o?z ?d, /rz e< rz e< ,?y/ ?s ?s ?s ?sd ]p]?o(]o?? ?s ?s dk^/l^u^ functional overview stm32f756xx 12/108 docid026379 rev 2 2 functional overview 2.1 arm ? cortex ? -m7 with fpu the arm ? cortex ? -m7 with fpu processor is the latest generation of arm processors for embedded systems. it was developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and low interrupt latency. the cortex ? -m7 processor is a highly efficient high-performance featuring: ? six-stage dual-issue pipeline ? dynamic branch prediction ? harvard caches (4kb of i-cache and 4kb of d-cache) ? 64-bit axi4 interface ? 64-bit itcm interface ? 2x32-bit dtcm interfaces the processor supports the following memory interfaces: ? tightly coupled memory (tcm) interface. ? harvard instruction and data caches and axi master (axim) interface. ? dedicated low-latency ahb-lite peripheral (ahbp) interface. the processor supports a set of dsp instructions which allow efficient signal processing and complex algorithm execution. its single precision fpu (floating point unit ) speeds up software development by using metalanguage development tools, while avoiding saturation. figure 2 shows the general block diagram of the stm32f756xx family. note: cortex ? -m7 with fpu core is binary compatible with the cortex ? -m4 core. 2.2 memory protection unit the memory protection unit (mpu) is used to manage the cpu accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. this memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. the protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. the mpu is especially helpful for applications wh ere some critical or ce rtified code has to be protected against the misbehavior of other ta sks. it is usually managed by an rtos (real- time operating system). if a prog ram accesses a memory location that is prohibited by the mpu, the rtos can detect it and take action. in an rtos environment, the kernel can dynamically update the mpu area setting, based on the process to be executed. the mpu is optional and can be bypassed for applications that do not need it.
docid026379 rev 2 13/108 stm32f756xx functional overview 38 2.3 embedded flash memory the stm32f756xx devices embed a flash memory of up to 1 mbytes available for storing programs and data. 2.4 crc (cyclic redundancy check) calculation unit the crc (cyclic redundancy check) calculati on unit is used to get a crc code using a configurable generator polynomial value and size. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the crc calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at link- time and stored at a given memory location. 2.5 embedded sram all devices features: ? system sram up to 320kbytes : ? sram1 on ahb bus matrix: 240kbytes ? sram2 on ahb bus matrix: 16kbytes ? dtcm-ram on tcm interface (tighly coupl ed memory interface): 64 kbytes for critical real time data. ? instruction ram (itcm-ram) 16kbytes: ? it is mapped on tcm interface and rese rved only for cpu execution/instruction useful for critical real time routines. the data tcm ram is accessible by the gp-d mas and peripherals dmas through specific ahb slave of the cpu.the instruction tcm ram is reserved only for cpu. it is accessed at cpu clock speed with 0 wait states. ? 4 kbytes of backup sram this area is accessible only from the cpu. its content is protected against possible unwanted write accesses, and is retained in standby or v bat mode. 2.6 axi-ahb bus matrix the stm32f756xx system architecture is based on 2 sub-systems : ? an axi to multi ahb bridge converting axi4 protocol to ahb-lite protocol: ? 3x axi to 32-bit ahb bridges connected to ahb bus matrix ? 1x axi to 64-bit ahb bridge connected to the embedded flash ? a multi-ahb bus-matrix ? the 32-bit multi-ahb bu s matrix interconnects all the masters (cpu, dmas, ethernet, usb hs, lcd-tft, and dma2d) and the slaves (flash memory, ram, fmc, quad spi, ahb and apb peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously.
functional overview stm32f756xx 14/108 docid026379 rev 2 figure 3. stm32f756xx axi-ahb bus matrix architecture 1. the above figure has large wires for 64- bits bus and thin wires for 32-bits bus. 2.7 dma controller (dma) the devices feature two general-purpose dual-port dmas (dma1 and dma2) with 8 streams each. they are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripher al transfers. they fe ature dedicated fifos for apb/ahb peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (ahb/apb). the two dma controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. the two dma controllers also have a double buffering feature, which autom ates the use and switching of two memory buffers without requiring any special code. 069 zd}???rd ?d??]?r^ zd &>^, d ^zd ?e< ^zd? < , ??]?z? &d???vo du?o y^w/ ,w y/?} uo?]r, , w?]?z ddzd /ddzd dd /dd y/d < e< , ,>]?er]?? /dd w w? ,^ ,'&dfkh .% 'w d 'w d? d ?z?v? h^kd' ,^ dzw/ dzdd dzdd? dzw? d,zedzd h^z,^zd >rd&d z?}urzd >rd&dzd d? o??}? ~d?
docid026379 rev 2 15/108 stm32f756xx functional overview 38 each stream is connected to dedicated hardware dma requests, with support for software trigger on each stream. configuration is made by software and transfer sizes between source and destination are independent. the dma can be used with the main peripherals: ? spi and i 2 s ? i 2 c ? usart ? general-purpose, basic and advanced-control timers timx ? dac ? sdmmc ? cryptographic acceleration ? camera interface (dcmi) ? adc ? sai ? spdif-rx ? quad spi ? hdmi-cec 2.8 flexible memory controller (fmc) the flexible memory controller (fmc) includes three memory controllers: ? the nor/psram memory controller ? the nand/memory controller ? the synchronous dram (sdram/m obile lpsdr sdram) controller the main features of the fmc controller are the following: ? interface with static-memory mapped devices including: ? static random access memory (sram) ? nor flash memory/onenand flash memory ? psram (4 memory banks) ? nand flash memory with ecc hardware to check up to 8 kbytes of data ? interface with synchronous dram (sdr am/mobile lpsdr sdram) memories ? 8-,16-,32-bit data bus width ? independent chip select control for each memory bank ? independent configuration for each memory bank ? write fifo ? read fifo for sdram controller ? the maximum fmc_clk/fmc_sdclk frequen cy for synchronous accesses is hclk/2.
functional overview stm32f756xx 16/108 docid026379 rev 2 lcd parallel interface the fmc can be configured to interface seamlessly with most graphic lcd controllers. it supports the intel 8080 and motorola 6800 modes, and is flexible enough to adapt to specific lcd interfaces. this lcd parallel inte rface capability makes it easy to build cost- effective graphic applications using lcd modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration. 2.9 quad spi memory interface (quadspi) all stm32f75xx devices embed a quad spi memory interface, which is a specialized communication interface targetting single, dual or quad spi flash memories. it can work in: ? direct mode through registers ? external flash status register polling mode ? memory mapped mode. up to 256 mbytes external flash are memory mapped, supporting 8, 16 and 32-bit access. code execution is supported. the opcode and the frame format are fully pr ogrammable. communication can be either in single data rate or dual data rate. 2.10 lcd-tft controller the lcd-tft display controller provides a 24-b it parallel digital rgb (red, green, blue) and delivers all signals to interface directly to a broad range of lcd and tft panels up to xga (1024x768) resolution with the following features: ? 2 displays layers with dedicated fifo (64x32-bit) ? color look-up table (clut) up to 256 colors (256x24-bit) per layer ? up to 8 input color formats selectable per layer ? flexible blending between two layers us ing alpha value (per pixel or constant) ? flexible programmable parameters for each layer ? color keying (transparency color) ? up to 4 programmable interrupt events. 2.11 chrom-art accelerator? (dma2d) the chrom-art accelerator? (dma2d) is a graphic accelerator which offers advanced bit blitting, row data copy and pixel format conv ersion. it supports the following functions: ? rectangle filling with a fixed color ? rectangle copy ? rectangle copy with pixel format conversion ? rectangle composition with blending and pixel format conversion. various image format coding are supported, from indirect 4bpp color mode up to 32bpp direct color. it embeds dedicated memory to store color lookup tables.
docid026379 rev 2 17/108 stm32f756xx functional overview 38 an interrupt can be generated when an operation is complete or at a programmed watermark. all the operations are fully automatized and are running independently from the cpu or the dmas. 2.12 nested vectored inter rupt controller (nvic) the devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 97 maskable interrupt channels plus the 16 interrupt lines of the cortex ? - m7 with fpu core. ? closely coupled nvic gives low-latency interrupt processing ? interrupt entry vector table address passed directly to the core ? allows early processing of interrupts ? processing of late arriving, higher-priority interrupts ? support tail chaining ? processor state automatically saved ? interrupt entry restored on interrupt exit with no instruction overhead this hardware block provides flexible interrupt management features with minimum interrupt latency. 2.13 external interrupt/ event controller (exti) the external interrupt/event controller consists of 24 edge-detector lines used to generate interrupt/event requests. each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. a pending register maintains the status of the interrupt requests. the exti can detect an external line with a pulse width shorter than the internal apb2 clock period. up to 168 gpios can be connected to the 16 external interrupt lines. 2.14 clocks and startup on reset the 16 mhz internal hsi rc oscillator is selected as the default cpu clock. the 16 mhz internal rc oscillator is factory-trimmed to offer 1% accuracy. the application can then select as system clock either the rc osc illator or an external 4-26 mhz clock source. this clock can be monitored for failure. if a fa ilure is detected, the system automatically switches back to the inte rnal rc oscillator and a software in terrupt is genera ted (if enabled). this clock source is input to a pll thus allowing to increase the frequency up to 200 mhz. similarly, full interrupt management of the pll clock entry is available when necessary (for example if an indirectly us ed external oscillator fails). several prescalers allow t he configuration of the two ahb buses, the high-speed apb (apb2) and the low-sp eed apb (apb1) domains. the maxi mum frequency of the two ahb buses is 200 mhz while the maximum frequency of the high-speed apb domains is 100 mhz. the maximum allowe d frequency of the low-speed apb domain is 50 mhz. the devices embed two dedicated pll (plli2s and pllsai) which allow to achieve audio class performance. in this case, the i 2 s and sai master clock can generate all standard sampling frequencies from 8 khz to 192 khz.
functional overview stm32f756xx 18/108 docid026379 rev 2 2.15 boot modes at startup, the boot memory space is sele cted by the boot pin and boot_addx option bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3fff ffff which includes: ? all flash address space mapped on itcm or axim interface ? all ram address space: itcm, dtcm rams and srams mapped on axim interface ? the system memory bootloader the boot loader is located in system memory. it is used to reprogram the flash memory through a serial interface. 2.16 power supply schemes ? v dd = 1.7 to 3.6 v: external power supply for i/os and the internal regulator (when enabled), provided externally through v dd pins. ? v ssa , v dda = 1.7 to 3.6 v: external analog power supplies for adc, dac, reset blocks, rcs and pll. v dda and v ssa must be connected to v dd and v ss , respectively. ? vddusb can be connected either to vdd or an external independent power supply (3.0 to 3.6v) for usb transceivers. for exam ple, when device is powered at 1.8v, an independent power supply 3.3v can be connected to vddusb. ? v bat = 1.65 to 3.6 v: power supply for rtc, external clock 32 khz oscillator and backup registers (through power switch) when v dd is not present. note: v dd /v dda minimum value of 1.7 v is obtained when the internal reset is off (refer to section 2.17.2: internal reset off ). refer to table 3: voltage regulator configuration mode versus device operating mode to identify the packages supporting this option. 2.17 power supply supervisor 2.17.1 internal reset on on packages embedding the pdr_on pin, th e power supply supervisor is enabled by holding pdr_on high. on the other packa ges, the power supply supervisor is always enabled. the device has an integrated power-on reset (por)/ power-down reset (pdr) circuitry coupled with a brownout reset (bor) circuitry. at power-on, por/pdr is always active and ensures proper operation starting from 1.8 v. after the 1.8 v por threshold level is reached, the option byte loading process star ts, either to confirm or modify default bor thresholds, or to disable bor permanently. three bor thresholds are available through option bytes. the device remains in reset mode when v dd is below a specified threshold, v por/pdr or v bor , without the need for an external reset circuit. the device also features an embedded programmable voltage detector (pvd) that monitors the v dd /v dda power supply and compares it to the v pvd threshold. an interrupt can be generated when v dd /v dda drops below the v pvd threshold and/or when v dd /v dda is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software.
docid026379 rev 2 19/108 stm32f756xx functional overview 38 2.17.2 internal reset off this feature is available only on packages featuring the pdr_on pin. the internal power-on reset (por) / power-down reset (pdr) circui try is disabled through the pdr_on pin. an external power supply supervisor should monitor v dd and nrst and should maintain the device in reset mode as long as v dd is below a specified threshold. pdr_on should be connected to v ss . refer to figure 4: power supply supervisor interconnection with internal reset off . figure 4. power supply supervisor interconnection with internal reset off the v dd specified threshold, below which the device must be maintained under reset, is 1.7 v (see figure 5 ). a comprehensive set of power-saving mode allows to design low-power applications. when the internal reset is off, the following integrated features are no more supported: ? the integrated power-on reset (por) / power-down reset (pdr) circuitry is disabled ? the brownout reset (bor) circuitry must be disabled ? the embedded programmable voltage detector (pvd) is disabled ? v bat functionality is no more available and v bat pin should be connected to v dd . all packages, except for the lqfp100, allow to disable the internal reset through the pdr_on signal when connected to v ss . 069 1567 9 '' 3'5b21 ([whuqdo9 '' srzhuvxsso\vxshuylvru ([wuhvhwfrqwuroohudfwlyhzkhq 9 '' 9 9 '' $ssolfdwlrquhvhw vljqdo 9 66
functional overview stm32f756xx 20/108 docid026379 rev 2 figure 5. pdr_on control with internal reset off 2.18 voltage regulator the regulator has four operating modes: ? regulator on ? main regulator mode (mr) ? low power regulator (lpr) ? power-down ? regulator off 2.18.1 regulator on on packages embedding the bypass_reg pin, the regulator is enabled by holding bypass_reg low. on all ot her packages, the regula tor is always enabled. there are three power modes configured by software when the regulator is on: ? mr mode used in run/sleep modes or in stop modes ? in run/sleep mode the mr mode is used either in the normal mode (default mode) or the over-drive mode (enabled by software). different voltages scaling are provided to reach the best compromise between maximum frequency and dynamic power consumption. 069 9 '' wlph 3'5 9 wlph 1567 3'5b21 3'5b21 5hvhwe\rwkhuvrxufhwkdq srzhuvxsso\vxshuylvru
docid026379 rev 2 21/108 stm32f756xx functional overview 38 the over-drive mode allows operating at a higher frequency than the normal mode for a given voltage scaling. ? in stop modes the mr can be configured in two ways during stop mode: mr operates in normal mode (default mode of mr in stop mode) mr operates in under-drive mode (reduced leakage mode). ? lpr is used in the stop modes: the lp regulator mode is configured by software when entering stop mode. like the mr mode, the lpr can be configured in two ways during stop mode: ? lpr operates in normal mode (default mode when lpr is on) ? lpr operates in under-drive mode (reduced leakage mode). ? power-down is used in standby mode. the power-down mode is activated only when entering in standby mode. the regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption. the contents of th e registers and sram are lost. refer to table 3 for a summary of voltage regulator modes versus device operating modes. two external ceramic capacitors should be connected on v cap_1 and v cap_2 pin. all packages have the regulator on feature. 2.18.2 regulator off this feature is availa ble only on packages fe aturing the bypass_reg pi n. the regulator is disabled by holding bypass_reg high. the regulator off mode allows to supply externally a v 12 voltage source through v cap_1 and v cap_2 pins. since the internal voltage scaling is not managed internally, the external voltage value must be aligned with the targeted maximum frequency.the two 2.2 f ceramic capacitors should be replaced by two 100 nf decoupling capacitors. when the regulator is off, there is no more internal monitoring on v 12 . an external power supply supervisor should be used to monitor the v 12 of the logic power domain. pa0 pin should be used for this purpose, and act as power-on reset on v 12 power domain. table 3. voltage regulator configuration mode versus device operating mode (1) 1. ?-? means that the corresponding configuration is not available. voltage regulator configuration run mode sleep mode stop mode standby mode normal mode mr mr mr or lpr - over-drive mode (2) 2. the over-drive mode is not available when v dd = 1.7 to 2.1 v. mr mr - - under-drive mode - - mr or lpr - power-down mode ---yes
functional overview stm32f756xx 22/108 docid026379 rev 2 in regulator off mode, the following features are no more supported: ? pa0 cannot be used as a gpio pin sinc e it allows to reset a part of the v 12 logic power domain which is not reset by the nrst pin. ? as long as pa0 is kept low, the debug mode cannot be used under power-on reset. as a consequence, pa0 and nrst pins must be managed separately if the debug connection under reset or pre-reset is required. ? the over-drive and under-drive modes are not available. ? the standby mode is not available. figure 6. regulator off the following conditions must be respected: ? v dd should always be higher than v cap_1 and v cap_2 to avoid current injection between power domains. ? if the time for v cap_1 and v cap_2 to reach v 12 minimum value is faster than the time for v dd to reach 1.7 v, then pa0 should be k ept low to cover both conditions: until v cap_1 and v cap_2 reach v 12 minimum value and until v dd reaches 1.7 v (see figure 7 ). ? otherwise, if the time for v cap_1 and v cap_2 to reach v 12 minimum value is slower than the time for v dd to reach 1.7 v, then pa0 could be asserted low externally (see figure 8 ). ? if v cap_1 and v cap_2 go below v 12 minimum value and v dd is higher than 1.7 v, then a reset must be asserted on pa0 pin. note: the minimum value of v 12 depends on the maximum frequency targeted in the application. dl9 %<3$66b5(* 9 &$3b 9 &$3b 3$ 9 9 '' 1567 9 '' $ssolfdwlrquhvhw vljqdorswlrqdo ([whuqdo9 &$3b srzhu vxsso\vxshuylvru ([wuhvhwfrqwuroohudfwlyh zkhq9 &$3b 0lq9 9
docid026379 rev 2 23/108 stm32f756xx functional overview 38 figure 7. startup in regulator off: slow v dd slope - power-down reset risen after v cap_1 /v cap_2 stabilization 1. this figure is valid whatever the internal reset mode (on or off). figure 8. startup in regulator off mode: fast v dd slope - power-down reset risen before v cap_1 /v cap_2 stabilization 1. this figure is valid whatever the internal reset mode (on or off). dli 9 '' wlph 0lq9 3'5 9ru9 9 &$3b 9 &$3b 9 1567 wlph 9 '' wlph 0lq9 9 &$3b 9 &$3b 9 3$dvvhuwhgh[whuqdoo\ 1567 wlph dlh 3'5 9ru9
functional overview stm32f756xx 24/108 docid026379 rev 2 2.18.3 regulator on/off and inte rnal reset on/off availability 2.19 real-time clock (rtc), back up sram and backup registers the rtc is an independent bcd timer/count er. it supports the following features: ? calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in bcd (binary-coded decimal) format. ? automatic correction for 28, 29 (leap ye ar), 30, and 31 days of the month. ? two programmable alarms. ? on-the-fly correction from 1 to 32767 rtc clock pulses. this can be used to synchronize it with a master clock. ? reference clock detection: a more precise se cond source clock (50 or 60 hz) can be used to enhance the calendar precision. ? digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal inaccuracy. ? three anti-tamper detection pins with programmable filter. ? timestamp feature which can be used to save the calendar content. this function can be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to v bat mode. ? 17-bit auto-reload wakeup timer (wut) for periodic events with programmable resolution and period. the rtc and the 32 backup registers are supplied through a switch that takes power either from the v dd supply when present or from the v bat pin. the backup registers are 32-bit registers used to store 128 bytes of user application data when v dd power is not present. they are not reset by a system or power reset, or when the device wakes up from standby mode. the rtc clock sources can be: ? a 32.768 khz external crystal (lse) ? an external resonator or oscillator(lse) ? the internal low power rc oscillator (l si, with typical frequency of 32 khz) ? the high-speed external clock (hse) divided by 32. table 4. regulator on/off and in ternal reset on/off availability package regulator on regulator off internal reset on internal reset off lqfp100 yes no yes no lqfp144, lqfp208 yes pdr_on set to v dd yes pdr_on set to vss lqfp176, wlcsp143, ufbga176, tfbga216 yes bypass_reg set to v ss yes bypass_reg set to v dd
docid026379 rev 2 25/108 stm32f756xx functional overview 38 the rtc is functional in v bat mode and in all lo w-power modes when it is clocked by the lse. when clocked by the lsi, the rtc is not functional in v bat mode, but is functional in all low-power modes. all rtc events (alarm, wakeup timer, timestamp or tamper) can generate an interrupt and wakeup the device from the low-power modes. 2.20 low-power modes the devices support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: ? sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. ? stop mode the stop mode achieves the lowest power consumption while retaining the contents of sram and registers. all clocks in the 1.2 v domain are stopped, the pll, the hsi rc and the hse crystal osc illators are disabled. the voltage regulator can be put either in main regulator mode (mr) or in low-power mode (lpr). both modes can be configured as follows (see table 5: voltage regulator modes in stop mode ): ? normal mode (default mode when mr or lpr is enabled) ? under-drive mode. the device can be woken up from the stop mo de by any of the exti line (the exti line source can be one of the 16 external lines , the pvd output, the rtc alarm / wakeup / tamper / time stamp events, the usb otg fs/hs wakeup or the ethernet wakeup and lptim1 asynchronous interrupt). ? standby mode the standby mode is used to achieve the lowest power consumption. the internal voltage regulator is switched off so that the entire 1.2 v domain is powered off. the pll, the hsi rc and the hse crystal oscillato rs are also switched off. after entering standby mode, the sram and register conten ts are lost except for registers in the backup domain and the backup sram when selected. the device exits the standby mode when an external reset (nrst pin), an iwdg reset, a rising or falling edge on one of the 6 wkup pins (pa0, pa2, pc1, pc13, pi8, pi11), or an rtc alarm / wakeup / tamper /time stamp event occurs. the standby mode is not supported when the embedded voltage regulator is bypassed and the 1.2 v domain is controlled by an external power. table 5. voltage regulator modes in stop mode voltage regulator configuration main regulator (mr) low-power regulator (lpr) normal mode mr on lpr on under-drive mode mr in under-dri ve mode lpr in under-drive mode
functional overview stm32f756xx 26/108 docid026379 rev 2 2.21 v bat operation the v bat pin allows to power the device v bat domain from an external battery, an external supercapacitor, or from v dd when no external battery and an external supercapacitor are present. v bat operation is activated when v dd is not present. the v bat pin supplies the rtc, the backup registers and the backup sram. note: when the microcontroller is supplied from v bat , external interrupts and rtc alarm/events do not exit it from v bat operation. when pdr_on pin is connected to v ss (internal reset off), the v bat functionality is no more available and v bat pin should be connected to v dd . 2.22 timers and watchdogs the devices include two advanced-control time rs, eight general-purpose timers, two basic timers and two watchdog timers. all timer counters can be frozen in debug mode. table 6 compares the features of the advanced-c ontrol, general-purpose and basic timers.
docid026379 rev 2 27/108 stm32f756xx functional overview 38 2.22.1 advanced-control timers (tim1, tim8) the advanced-control timers (tim1, tim8) can be seen as three-phase pwm generators multiplexed on 6 channels. they have complementary pwm outputs with programmable table 6. timer feature comparison timer type timer counter resolution counter type prescaler factor dma request generation capture/ compare channels complem entary output max interfac e clock (mhz) max timer clock (mhz) (1) advance d-control tim1, tim8 16-bit up, down, up/down any integer between 1 and 65536 yes 4 yes 100 200 general purpose tim2, tim5 32-bit up, down, up/down any integer between 1 and 65536 yes 4 no 50 100/200 tim3, tim4 16-bit up, down, up/down any integer between 1 and 65536 yes 4 no 50 100/200 tim9 16-bit up any integer between 1 and 65536 no 2 no 100 200 tim10, tim11 16-bit up any integer between 1 and 65536 no 1 no 100 200 tim12 16-bit up any integer between 1 and 65536 no 2 no 50 100/200 tim13, tim14 16-bit up any integer between 1 and 65536 no 1 no 50 100/200 basic tim6, tim7 16-bit up any integer between 1 and 65536 yes 0 no 50 100/200 1. the maximum timer clock is either 100 or 200 mhz depending on timpre bit configuration in the rcc_dckcfgr register.
functional overview stm32f756xx 28/108 docid026379 rev 2 inserted dead times. they can also be considered as complete general-purpose timers. their 4 independent channels can be used for: ? input capture ? output compare ? pwm generation (edge- or center-aligned modes) ? one-pulse mode output if configured as standard 16-bit timers, they ha ve the same features as the general-purpose timx timers. if configured as 16-bit pwm generators, they have full modulation capability (0- 100%). the advanced-control timer can work togethe r with the timx timers via the timer link feature for synchronizat ion or event chaining. tim1 and tim8 support indepe ndent dma request generation. 2.22.2 general-purpose timers (timx) there are ten synchronizable general-purpose timers embedded in the stm32f756xx devices (see table 6 for differences). ? tim2, tim3, tim4, tim5 the stm32f756xx include 4 full-featured g eneral-purpose timers: tim2, tim5, tim3, and tim4.the tim2 and tim5 timers are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. the tim3 and tim4 timers are based on a 16- bit auto-reload up/downcounter and a 16-bit prescaler. they all feature 4 independent channels for input capture/ou tput compare, pwm or one-pul se mode output. this gives up to 16 input capture/output comp are/pwms on the largest packages. the tim2, tim3, tim4, tim5 general-purpose timers can work together, or with the other general-purpose timers and the advanc ed-control timers tim1 and tim8 via the timer link feature for synchronization or event chaining. any of these general-purpose timers can be used to generate pwm outputs. tim2, tim3, tim4, tim5 all have indepen dent dma request generation. they are capable of handling quadrature (incremental ) encoder signals and the digital outputs from 1 to 4 hall-effect sensors. ? tim9, tim10, tim11, ti m12, tim13, and tim14 these timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. tim10, tim11, tim13, and tim14 feature one independent channel, whereas tim9 and tim12 have two independent channels fo r input capture/output compare, pwm or one-pulse mode output. they can be synchronized with the tim2, tim3, tim4, tim5 full-featured general-purpose timers. they can also be used as simple time bases. 2.22.3 basic timers tim6 and tim7 these timers are mainly used for dac trigger and waveform generation. they can also be used as a generic 16-bit time base. tim6 and tim7 support indepe ndent dma request generation. 2.22.4 low-power timer (lptim1) the low-power timer has an independent clock and is running also in stop mode if it is clocked by lse, lsi or an external clock. it is able to wakeup the devices from stop mode.
docid026379 rev 2 29/108 stm32f756xx functional overview 38 this low-power timer supports the following features: ? 16-bit up counter with 16-bit autoreload register ? 16-bit compare register ? configurable output: pulse, pwm ? continuous / one-shot mode ? selectable software / hardware input trigger ? selectable clock source: ? internal clock source: l se, lsi, hsi or apb clock ? external clock source over lptim input (working even with no internal clock source running, used by the pulse counter application) ? programmable digital glitch filter ? encoder mode 2.22.5 independent watchdog the independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. it is clocked from an independent 32 khz internal rc and as it operates independently from the main clock, it can operate in stop and stan dby modes. it can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. it is hardware- or software-configurable through the option bytes. 2.22.6 window watchdog the window watchdog is based on a 7-bit downcounter that can be set as free-running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the main clock. it has an early warning interrupt capab ility and the counter can be frozen in debug mode. 2.22.7 systick timer this timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. it features: ? a 24-bit downcounter ? autoreload capability ? maskable system interrupt generation when the counter reaches 0 ? programmable clock source. 2.23 inter-integrated circuit interface (i 2 c) the device embeds 4 i2c. refer to table table 7: i2c implementation for the features implementation. the i 2 c bus interface handles communications bet ween the microcontroller and the serial i 2 c bus. it co ntrols all i 2 c bus-specific sequencing, protocol, arbitration and timing.
functional overview stm32f756xx 30/108 docid026379 rev 2 the i2c peripheral supports: ? i 2 c-bus specification and user manual re v. 5 compatibility: ? slave and master modes , multimaster capability ? standard-mode (sm), with a bitrate up to 100 kbit/s ? fast-mode (fm), with a bitrate up to 400 kbit/s ? 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses ? programmable setup and hold times ? optional clock stretching ? system management bus (smbus) spec ification rev 2.0 compatibility: ? hardware pec (packet error checking) generation and verification with ack control ? address resolution protocol (arp) support ? smbus alert ? power system management protocol (pmbus tm ) specification rev 1.1 compatibility ? independent clock: a choice of independent clock sources allowing the i2c communication speed to be independent from the pclk reprogramming. ? programmable analog and digital noise filters ? 1-byte buffer with dma capability 2.24 universal synchronous/asynch ronous receiver transmitters (usart) the device embeds usart. refer to ta b l e 8: usart implementation for the features implementation. the universal synchronous asynchronous receiver transmitter (usart) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard nrz asynchronous serial data format. table 7. i2c implementation i2c features (1) 1. x: supported i2c1 i2c2 i2c3 i2c4 standard-mode (up to 100 kbit/s) x x x x fast-mode (up to 400 kbit/s) x x x x programmable analog and digital noise filters x x x x smbus/pmbus hardware support x x x x independent clock x x x x
docid026379 rev 2 31/108 stm32f756xx functional overview 38 the usart peripheral supports: ? full-duplex asynchronous communications ? configurable oversamp ling method by 16 or 8 to gi ve flexibility be tween speed and clock tolerance ? dual clock domain allowing convenient baud rate programming independent from the pclk reprogramming ? a common programmable transmit and receive baud rate of up to 12.5 mbit/s when the clock frequency is 100 mhz and oversampling is by 8. ? auto baud rate detection ? programmable data word length (7 or 8 or 9 bits) word length ? programmable data order with msb-first or lsb-first shifting ? progarmmable parity (odd, even, no parity) ? configurable stop bits (1 or 1.5 or 2 stop bits) ? synchronous mode and clock output for synchronous communications ? single-wire half-duplex communications ? separate signal polarity control for transmission and reception ? swappable tx/rx pin configuration ? hardware flow control for mo dem and rs-485 transceiver ? multiprocessor communications ? lin master synchronous break send capability and lin slav e break detection capability ? irda sir encoder decoder supporting 3/16 bit duration for normal mode ? smartcard mode ( t=0 and t=1 asynchronous protocols for smartcards as defined in the iso/iec 7816-3 standard ) ? support for modbus communication the table below summarizes the implementation of all u(s)arts instances table 8. usart implementation features (1) usart1/2/3/6 uart4/5/7/8 data length 7, 8 and 9 bits hardware flow control for modem x x continuous communication using dma x x multiprocessor communication x x synchronous mode x smartcard mode x single-wire half-duplex communication x x irda sir endec block x x lin mode x x dual clock domain x x receiver timeout interrupt x x modbus communication x x
functional overview stm32f756xx 32/108 docid026379 rev 2 2.25 serial peripheral interface (spi)/inter- integrated sound interfaces (i2s) the devices feature up to six spis in slave and master modes in full-duplex and simplex communication modes. spi1, spi4, spi5, and spi6 can communicate at up to 50 mbits/s, spi2 and spi3 can communicate at up to 25 mbit/s. the 3-bit prescaler gives 8 master mode frequencies and the frame is configurable from 4 to 16 bits. the spi interfaces support nss pulse mode, ti mode and hardware crc calculation. all spis can be served by the dma controller. three standard i 2 s interfaces (multiplexed with spi1, spi2 and spi3) are available. they can be operated in master or slave mode, in simplex communication modes, and can be configured to operate with a 16-/32-bit reso lution as an input or output channel. audio sampling frequencies from 8 khz up to 192 khz are supported. when either or both of the i 2 s interfaces is/are configured in master mo de, the master clock can be output to the external dac/codec at 256 ti mes the sampling frequency. all i2sx can be served by the dma controller. 2.26 serial audio interface (sai) the devices embed two serial audio interfaces. the serial audio interface is based on two independent audio subblocks which can operate as transmitter or receiver with their fifo. many audio protocols are supported by each block: i2s standards, lsb or msb-justifie d, pcm/dsp, tdm, ac?97 and spdif output, supporting audio sampling freq uencies from 8 khz up to 19 2 khz. both subblocks can be configured in master or in slave mode. in master mode, the master clock can be output to the external dac/codec at 256 times of the sampling frequency. the two sub-blocks can be configured in synchronous mode when full-duplex mode is required. sai1 and sai2 can be served by the dma controller 2.27 spdif-rx receiver interface (spdif-rx) the spdif-rx peripheral, is designed to receiv e an s/pdif flow compliant with iec-60958 and iec-61937. these standards support simple stereo streams up to high sample rate, and compressed multi-channel surround sound, such as those defined by dolby or dts (up to 5.1). auto baud rate detection x x driver enable x x 1. x: supported table 8. usart implementation (continued) features (1) usart1/2/3/6 uart4/5/7/8
docid026379 rev 2 33/108 stm32f756xx functional overview 38 the main features of the spdif-rx are the following: ? up to 4 inputs available ? automatic symbol rate detection ? maximum symbol rate: 12.288 mhz ? stereo stream from 32 to 192 khz supported ? supports audio iec-60958 and iec-61937, consumer applications ? parity bit management ? communication using dma for audio samples ? communication using dma for contro l and user channel information ? interrupt capabilities the spdif-rx receiver provides all the necessary features to detect the symbol rate, and decode the incoming data stream. the user can select the wanted spdif input, and when a valid signal will be available, the spdif-rx will re-sample the incoming signal, decode the manchester stream, recognize frames, sub-frames and blocks elements. it delivers to the cpu decoded data, and associated status flags. the spdif-rx also offers a signal named spdif_frame_sync, which toggles at the s/pdif sub-frame rate that will be used to compute the exact samp le rate for clock drift algorithms. 2.28 audio pll (plli2s) the devices feature an additional dedicated pll for audio i 2 s and sai applications. it allows to achieve error-free i 2 s sampling clock accuracy witho ut compromising on the cpu performance, while using usb peripherals. the plli2s configuration can be modified to manage an i 2 s/sai sample rate change without disabling the main pll (pll) used for cpu, usb and ethernet interfaces. the audio pll can be programmed with very low error to obtain sampling rates ranging from 8 khz to 192 khz. in addition to the audio pll, a master clock input pin can be used to synchronize the i 2 s/sai flow with an external pll (or codec output). 2.29 audio and lcd pll(pllsai) an additional pll dedicated to audio and lc d-tft is used for sai1 peripheral in case the plli2s is programmed to achieve another audio sampling frequency (49.152 mhz or 11.2896 mhz) and the audio application requires both sampling frequencies simultaneously. the pllsai is also used to generate the lcd-tft clock. 2.30 sd/sdio/mmc card ho st interface (sdmmc) an sdmmc host interface is available, that su pports multimediacard system specification version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.
functional overview stm32f756xx 34/108 docid026379 rev 2 the interface allows data transfer at up to 50 mhz, and is compliant with the sd memory card specification version 2.0. the sdmmc card specification version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. the current version supports only one sd/s dmmc/mmc4.2 card at any one time and a stack of mmc4.1 or previous. the sdmmc can be served by the dma controller 2.31 ethernet mac interface with dedicated dma and ieee 1588 support the devices provide an ieee- 802.3-2002-compliant media access controller (mac) for ethernet lan communications through an industry-standard medium-independent interface (mii) or a reduced medium-independent interfac e (rmii). the microcontroller requires an external physical interface device (phy) to co nnect to the physical lan bus (twisted-pair, fiber, etc.). the phy is connec ted to the device mii port using 17 signals for mii or 9 signals for rmii, and can be clocked using the 25 mhz (mii) from the microcontroller. the devices include the following features: ? supports 10 and 100 mbit/s rates ? dedicated dma controller allowing high-speed transfers between the dedicated sram and the descriptors ? tagged mac frame support (vlan support) ? half-duplex (csma/cd) and full-duplex operation ? mac control sublayer (control frames) support ? 32-bit crc generation and removal ? several address filtering modes for physic al and multicast address (multicast and group addresses) ? 32-bit status code for each transmitted or received frame ? internal fifos to buffer transmit and receive frames. the transmit fifo and the receive fifo are both 2 kbytes. ? supports hardware ptp (precision time protocol) in accordance with ieee 1588 2008 (ptp v2) with the time stamp compar ator connected to the tim2 input ? triggers interrupt when system time becomes greater than target time 2.32 controller area network (bxcan) the two cans are compliant with the 2.0a and b (a ctive) specifications with a bitrate up to 1 mbit/s. they can receive and transmit standard frames with 11-bit id entifiers as well as extended frames with 29-bit identifiers. each can has three transmit mailboxes, two receive fifos with 3 stages and 28 shared scalable filter banks (all of them can be used even if one can is used). 256 bytes of sram are allocated for each can.
docid026379 rev 2 35/108 stm32f756xx functional overview 38 2.33 universal serial bus on -the-go full-speed (otg_fs) the device embeds an usb otg full-speed de vice/host/otg peripher al with integrated transceivers. the usb otg fs peripheral is compliant with the usb 2.0 specification and with the otg 2.0 specification. it has software-configurable endpoint setting and supports suspend/resume. the usb otg controller requires a dedicat ed 48 mhz clock that is generated by a p ll connected to the hse oscillator. the major features are: ? combined rx and tx fifo size of 1.28 kb with dynamic fifo sizing ? supports the session request protocol (srp) and host negotiation protocol (hnp) ? 1 bidirectional control endpoint + 5 in endpoints + 5 out endpoints ? 12 host channels with periodic out support ? software configurable to otg1.3 and otg2.0 modes of operation ? usb 2.0 lpm (link power management) support ? internal fs otg phy support ? hnp/snp/ip inside (no need for any external resistor) for otg/host modes, a power switch is needed in case bus-powered devices are connected 2.34 universal serial bus on -the-go high-speed (otg_hs) the device embeds a usb otg high-speed (up to 480 mb/s) device/host/otg peripheral. the usb otg hs supports both full-speed and high-speed operations. it integrates the transceivers for full-speed operation (12 mb/s) and features a utmi low-pin interface (ulpi) for high-speed operation (480 mb/s). when using the usb otg hs in hs mode, an external phy device connecte d to the ulpi is required. the usb otg hs peripheral is compliant wit h the usb 2.0 specification and with the otg 2.0 specification. it has software-configurable endpoint setting and supports suspend/resume. the usb otg controller requires a dedicated 48 mhz clock that is generated by a p ll connected to the hse oscillator. the major features are: ? combined rx and tx fifo size of 4 kb with dynamic fifo sizing ? supports the session request protocol (srp) and host negotiation protocol (hnp) ? 8 bidirectional endpoints ? 16 host channels with periodic out support ? software configurable to otg1.3 and otg2.0 modes of operation ? usb 2.0 lpm (link power management) support ? internal fs otg phy support ? external hs or hs otg operation suppor ting ulpi in sdr mode. the otg phy is connected to the microcontroller ulpi port through 12 signals. it can be clocked using the 60 mhz output. ? internal usb dma ? hnp/snp/ip inside (no need for any external resistor) ? for otg/host modes, a power switch is needed in case bus-powered devices are connected
functional overview stm32f756xx 36/108 docid026379 rev 2 2.35 high-definition multimedia interface (hdmi) - consumer electronics control (cec) the device embeds a hdmi-cec controller that provides hardware support for the consumer electronics control (cec) protoc ol (supplement 1 to the hdmi standard). this protocol provides high-level control functions between all audiovisual products in an environment. it is specified to operate at low speeds with minimum processing and memory overhead. it has a clock domain independent from the cpu clock, allowing the hdmi-cec controller to wakeup the mcu from stop mode on data reception. 2.36 digital camera interface (dcmi) the devices embed a camera interface that can connect with camera modules and cmos sensors through an 8-bit to 14-bit parallel interface, to receive video data. the camera interface can sustain a data transfer rate up to 54 mbyte/s at 54 mhz. it features: ? programmable polarity for the input pixel clock and synchronization signals ? parallel data communication can be 8-, 10-, 12- or 14-bit ? supports 8-bit progressive video monochrome or raw bayer format, ycbcr 4:2:2 progressive video, rgb 565 progressive video or compressed data (like jpeg) ? supports continuous mode or snapshot (a single frame) mode ? capability to automatically crop the image 2.37 cryptograp hic acceleration the devices embed a cryptographic accelerator. this cryptographic accelerator provides a set of hardware acceleration for the advanced cryptographic algorithms usually needed to provide confidentiality, authentication, data in tegrity and non repudiation when exchanging messages with a peer. ? these algorithms consists of: encryption/decryption ? des/tdes (data encryption standard/triple data encryption standard): ecb (electronic codebook) and cbc (cipher block chaining) chaining algorithms, 64-, 128- or 192-bit key ? aes (advanced encryption standard): ecb, cbc, gcm, ccm, and ctr (counter mode) chaining algorithms, 128, 192 or 256-bit key universal hash ? sha-1 and sha-2 (secure hash algorithms) ?md5 ?hmac the cryptographic accelerator supports dma request generation. 2.38 random number generator (rng) all devices embed an rng that delivers 32-bi t random numbers generated by an integrated analog circuit.
docid026379 rev 2 37/108 stm32f756xx functional overview 38 2.39 general-purpose in put/outputs (gpios) each of the gpio pins can be configured by so ftware as output (push-pull or open-drain, with or without pull-up or pull-down), as input (f loating, with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions. all gpios are high-current -capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. the i/o configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the i/os registers. fast i/o handling a llowing maximum i/o toggling up to 100 mhz. 2.40 analog-to-digital converters (adcs) three 12-bit analog-to-digital converters are embedded and each adc shares up to 16 external channels, performing conversions in the single-shot or scan mode. in scan mode, automatic conversion is performed on a selected group of analog inputs. additional logic functions embedded in the adc interface allow: ? simultaneous sample and hold ? interleaved sample and hold the adc can be served by the dma controller. an analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. an interrupt is generated when the converted vo ltage is outside the programmed thresholds. to synchronize a/d conversion and timers, t he adcs could be triggered by any of tim1, tim2, tim3, tim4, tim5, or tim8 timer. 2.41 temperature sensor the temperature sensor has to generate a voltage that varies linearly with temperature. the conversion range is between 1.7 v and 3.6 v. the temperature sensor is internally connected to the same input channel as v bat , adc1_in18, which is used to convert the sensor output voltage into a digital value. when the temperature sensor and v bat conversion are enabled at the same time, only v bat conversion is performed. as the offset of the temperature sensor varies fr om chip to chip due to process variation, the internal temperature sensor is mainly suitab le for applications that detect temperature changes instead of absolute temperatures. if an accurate temperature reading is needed, then an external temperature sensor part should be used. 2.42 digital-to-analog converter (dac) the two 12-bit buffered dac channels can be used to convert two digital signals into two analog voltage signal outputs.
functional overview stm32f756xx 38/108 docid026379 rev 2 this dual digital interface supports the following features: ? two dac converters: one for each output channel ? 8-bit or 12-bit monotonic output ? left or right data alignment in 12-bit mode ? synchronized update capability ? noise-wave generation ? triangular-wave generation ? dual dac channel independent or simultaneous conversions ? dma capability for each channel ? external triggers for conversion ? input voltage reference v ref+ eight dac trigger inputs are used in the device. the dac channels are triggered through the timer update outputs that are also connected to different dma streams. 2.43 serial wire jtag debug port (swj-dp) the arm swj-dp interface is embedded, and is a combined jtag and serial wire debug port that enables either a serial wire debug or a jtag probe to be connected to the target. debug is performed using 2 pins only instead of 5 required by the jtag (jtag pins could be re-use as gpio with alternate function): the jtag tms and tck pins are shared with swdio and swclk, respectively, and a specific sequence on the tms pin is used to switch between jtag-dp and sw-dp. 2.44 embedded trace macrocell? the arm embedded trace macrocell provides a greater visibility of the instruction and data flow inside the cpu core by streaming compressed data at a very high rate from the stm32f756xx through a small number of etm pi ns to an external hardware trace port analyzer (tpa) device. the tpa is connected to a host co mputer using usb, ethernet, or any other high-speed channel. real-time instru ction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. tpa hardware is commercially available from common development tool vendors. the embedded trace macrocell operates wi th third party debugger software tools.
docid026379 rev 2 39/108 stm32f756xx pinouts and pin description 80 3 pinouts and pin description figure 9. stm32f756xx lqfp100 pinout 1. the above figure shows the package top view. ?? ?? ? ? ?? ?e ?? ?? ? ? ?? ?? ? ? ?? ?e ?? ?? ? ? ? ? ? ? e ? ? ? ? ? e ? ? ? ? ? ?? ?? ?e ?? ? e ? ? ? ? ? e ? ? ?? ?? ? ? ?? ?e ?? ?? ? w? w? we w? w werk^??z/e w?rk^??zkhd s^^ s w,rk^z/e w w w? w? s^^ sz&= s s s^^ sw? w? w? w w s^^ s we w w? w w? w? sw s s s^^ w w w? we w? w? w w w? w w ? ? ?? ?? ? ? ?? ?? ?e ?? ? ? ?? ?? e e e? e? ee e? e e e? e? ? d^?es >y&w w?red/zddw w,rk^zkhd wrt<hw w w? w? w? w w we w w? w? we w? w w w w? w s^^ w? w w? w? we w? w? w? w w? we w? w? w? w w w? w? w? we w w w? w? kkd w w w? we w? sd ez^d
pinouts and pin description stm32f756xx 40/108 docid026379 rev 2 figure 10. stm32f756xx wlcsp143 ballout the above figure shows the package bump view. 9%$7 3'5 b21 069 $ % & ' ( ) * + - . / 0 1 3( 3& 3& 3) 3) 3) 3+ 3& 95() 3$ %<3$66b 5(* 3( 3( 3( 3& 9'' 3) 3) 3+ 3& 966$ 9''$ 3& 3$ 3$ 3% 3% 3* 3* 3' 3' 3' 3& 9'' 3% 3% 3% 3* 3' 3' 3' 3& 3$ %227 3% 3% 3* 9'' 3' 3& 3$ 9'' 3( 3( 9'' 3$ 3$ 3$ 966 9&$3 b 3) 3( 966 9'' 3* 3& 3& 3$ 3$ 3) 3) 3) 3* 966 3' 3& 3& 3$ 3) 3) 9'' 3* 3* 3* 3* 3* 9''86% 1567 3& 966 3' 3' 3' 966 966 3* 3& 3) 3) 3* 3( 3% 3' 3' 3$ 3$ 3% 9'' 9'' 9'' 9'' 3( 3% 3' 3* 3$ 3$ 3% 3( 3( 3( 3' 9'' 3$ 3& 3) 3) 3( 3( 3% 3% 3' 3& 3% 3) 3* 3( 3( 3% 9&$3 b 3% 3*
docid026379 rev 2 41/108 stm32f756xx pinouts and pin description 80 figure 11. stm32f756xx lqfp144 pinout 1. the above figure shows the package top view. 6 $$ 0$2?/. 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0' 6 $$ 6 33 0' 0' 0' 0' 0' 0' 0$ 0$ 6 $$ 6 33 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! 0% 6 $$ 0% 6 33 0% 0% 0! 0% 0! 6"!4 0! 0# 0! 0# 0! 0# 0! 0& 0# 0& 0# 0& 0# 0& 0# 0& 6 $$53" 0& 6 33 6 33 0' 6 $$ 0' 0& 0' 0& 0' 0& 0' 0& 0' 0& 0' 0( 0$ 0( 0$ .234 6 $$ 0# 6 33 0# 0$ 0# 0$ 0# 0$ 6 33! 0$ 6 $$ 0$ 6 2%& 0$ 6 $$! 0" 0! 0" 0! 0" 0! 0" 0! 6 33 6 $$ 0! 0! 0! 0! 0# 0# 0" 0" 0" 0& 0& 6 $$ 0& 0& 0& 0' 0' 0% 0% 0% 6 33 6 $$ 0% 0% 0% 0% 0% 0% 0" 0" 6 $$ ,1&0 6 #!0? 6 33 aic 6 #!0?
pinouts and pin description stm32f756xx 42/108 docid026379 rev 2 figure 12. stm32f756xx lqfp176 pinout 1. the above figure shows the package top view. -36 0$2?/. 6 $$ 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0' 6 $$ 6 33 0' 0' 0' 0' 0' 0' 0$ 0$ 6 $$ 6 33 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0) 0) 0% 6 $$ 0% 6 33 0% 0% 0! 0% 0! 6"!4 0! 0) 0! 0# 0! 0# 0! 0& 0# 0& 0# 0& 0# 0& 0# 0& 6 $$53" 0& 6 33 0' 0' 0& 0' 0& 0' 0& 0' 0& 0' 0& 0' 0( 0$ 0( 0$ .234 6 $$ 0# 6 33 0# 0$ 0# 0$ 0# 0$ 0$ 0$ 62%& 0$ 0" 0! 0" 0! 0" 0! 0" 0! "90!33?2%' 6 $$ 0! 0! 0! 0! 0# 0# 0" 0" 0" 0& 0& 633 6 $$ 0& 0& 0& 0' 0' 0% 0% 0% 6 33 6 $$ 0% 0% 0% 0% 0% 0% 0" 0" 6 #!0? 6 $$ ,1&0 6 #!0? 0) 0! 0! 6 $$ 6 33 0) 0) 0) 0( 0( 0( 0( 0( 0( 0( 0( 0) 0) 0( 0( 0( 6 $$ 6 33 0( 0# 0) 0) 0) 633 0( 0( 6$$ 633 6$$ 6$$ 633! 6$$!
docid026379 rev 2 43/108 stm32f756xx pinouts and pin description 80 figure 13. stm32f756xx lqfp208 pinout 1. the above figure shows the package top view. 069 w/ w/ w/? w/e s s^^ w w w? w? w w w? we w? w'? w< w< wy&w?? ? ? ?? ?? ? ? ?? ?? ?e ?? ? ? ?? ?? e e e? e? ee e? e e e? e? ? ? ?? ?? ?e ?? ? ? ?? ?? ? ? e ? ? ? ? ? e ? ? ? ? ? ?? ?? ?e ?? ? ? ?? ?? ? ? ?? ?? ?e ?? ? ? ?? ?? ? ? e w? w? we w? w sd w/? w? we w? w/? w/ w/ s^^ s w& w& w&? w/? w/? w/e w&? w&e w&? s^^ s w& w& w&? w&? w& w, w, ez^d w w w? w? s s^^ sz&= s w w w? w,? w,? w,e w,? w? s^^ s w/? w/ w/ w,? w,e w,? s s^^ swz? w? w? w w w? w? w? w? w w sh^ s^^ w'? w' w' w'? w'e w'? w'? w pinouts and pin description stm32f756xx 44/108 docid026379 rev 2 figure 14. stm32f756xx ufbga176 ballout 1. the above figure shows the package top view. aid !0%0% 0% 0% 0" 0" 0' 0' 0" 0" 0$ 0# 0! 0! 0! "0%0% 0% 0" 0" 0" 0' 0' 0' 0' 0$ 0$ 0# 0# 0! # 6"!4 0) 0) 0) 0$2?/. 6$$ 6$$ 6$$ 6$$ 0' 0$ 0$ 0) 0) 0! $ 0# 0) 0) 0) "//4 633 633 633 0$ 0$ 0$ 0( 0) 0! % 0# 0& 0) 0) 0( 0( 0) 0! &0# 633 6$$ 0( 633 633 633 633 633 633 6#!0 0# 0! ' 0( 633 6$$ 0( 633 633 633 633 633 633 6$$ 0# 0# ( 0( 0& 0& 0( 633 633 633 633 633 633 6$$53" 0' 0# * .234 0& 0( 633 633 633 633 633 6$$ 6$$ 0' 0' + 0& 0& 0& 6$$ 633 633 633 633 633 0( 0' 0' 0' , 0& 0& 0& "90!33? 2%' 0( 0( 0$ 0' -633!0# 0& 0# 0# 0# 0" 0' 633 633 6#!0? 0( 0( 0( 0$ 0$ .62%& 0! 0! 0# 0& 0' 6$$ 6$$ 6$$ 0% 0( 0$ 0$ 0$ 062%& 0! 0! 0! 0# 0& 0& 0% 0% 0% 0% 0" 0" 0$ 0$ 2 6$$! 0! 0! 0" 0" 0& 0& 0% 0% 0% 0% 0" 0" 0" 0" 633 0!
docid026379 rev 2 45/108 stm32f756xx pinouts and pin description 80 figure 15. stm32f756xx tfbga216 ballout 1. the above figure shows the package top view. -36 ! 0% 0% 0% 0' 0% 0% 0" 0" 0" 0" 0$ 0# 0! 0! 0! " 0% 0% 0' 0" 0" 0" 0' 0' 0* 0* 0$ 0$ 0# 0# 0! # 6"!4 0) 0) 0+ 0+ 0+ 0' 0' 0* 0$ 0$ 0$ 0) 0) 0! $ 0# 0& 0) 0) 0) 0) 0+ 0+ 0' 0* 0$ 0$ 0( 0) 0! % 0# 0& 0) 0) 0$2? /. "//4 6$$ 6$$ 6$$ 6$$ 6#!0 0( 0( 0) 0! & 0# 633 0) 6$$ 6$$ 633 633 6$$ 0+ 0+ 0# 0! ' 0( 0& 0) 0) 6$$ 633 6$$53" 0* 0+ 0# 0# ( 0( 0) 0( 6$$ 633 633 6$$ 0* 0* 0' 0# * .234 0& 0( 0( 6$$ 633 633 6$$ 0* 0* 0' 0' + 0& 0& 0& 0( 6$$ 633 633 633 633 633 6$$ 0* 0$ 0" 0$ , 0& 0& 0& 0# "90!33 2%' 633 6$$ 6$$ 6$$ 6$$ 6#!0 0$ 0" 0$ 0$ - 633! 0# 0# 0# 0" 0& 0' 0& 0* 0$ 0$ 0' 0' 0* 0( . 62%& 0! 0! 0! 0# 0& 0' 0* 0% 0$ 0' 0' 0( 0( 0( 62%& 0! 0! 0! 0# 0& 0* 0& 0% 0% 0% 0" 0( 0( 0( 0! 0! 0" 0" 0* 0* 0% 0% 0% 0% 0% 0" 0" 0" 633 0& 0 2 6$$! 633 633 633
pinouts and pin description stm32f756xx 46/108 docid026379 rev 2 table 9. legend/abbreviations used in the pinout table name abbreviation definition pin name unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name pin type s supply pin i input only pin i/o input / output pin i/o structure ft 5 v tolerant i/o tta 3.3 v tolerant i/o directly connected to adc b dedicated boot pin rst bidirectional reset pin with weak pull-up resistor notes unless otherwise specified by a note, all i/os are set as floating inputs during and after reset alternate functions functions selected through gpiox_afr registers additional functions functions directly selected/enabl ed through peripheral registers table 10. stm32f756xx pin and ball definition pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions lqfp100 wlcsp143 lqfp144 ufbga176 lqfp176 lqfp208 tfbga216 1 d8 1 a2 1 1 a3 pe2 i/o ft - traceclk, spi4_sck, sai1_mclk_a, quadspi_bk1_io2, eth_mii_txd3, fmc_a23, eventout - 2 c10 2 a1 2 2 a2 pe3 i/o ft - traced0, sai1_sd_b, fmc_a19, eventout - 3 b11 3 b1 3 3 a1 pe4 i/o ft - traced1, spi4_nss, sai1_fs_a, fmc_a20, dcmi_d4, lcd_b0, eventout -
docid026379 rev 2 47/108 stm32f756xx pinouts and pin description 80 4 d9 4 b2 4 4 b1 pe5 i/o ft - traced2, tim9_ch1, spi4_miso, sai1_sck_a, fmc_a21, dcmi_d6, lcd_g0, eventout - 5 e8 5 b3 5 5 b2 pe6 i/o ft - traced3, tim1_bkin2, tim9_ch2, spi4_mosi, sai1_sd_a, sai2_mck_b, fmc_a22, dcmi_d7, lcd_g1, eventout - ------g6vsss-- - - ------f5vdds-- - - 6 c11 6 c1 6 6 c1 vbat s - - - - - - - d2 7 7 c2 pi8 i/o ft (2) (3) eventout rtc_tamp2/ rtc_ts,wkup3 7 d10 7 d1 8 8 d1 pc13 i/o ft (2) (3) eventout rtc_tamp1/ rtc_ts/rtc_out ,wkup2 8d118 e1 9 9 e1 pc14- osc32_i n(pc14) i/o ft (2) (3) eventout osc32_in 9e119 f11010f1 pc15- osc32_ out(pc 15) i/o ft (2) (3) eventout osc32_out ------f2vsss-- - - ------g5vdds-- - - - - - d3 11 11 e4 pi9 i/o ft - can1_rx, fmc_d30, lcd_vsync, eventout - - - - e3 12 12 d5 pi10 i/o ft - eth_mii_rx_er, fmc_d31, lcd_hsync, eventout - table 10. stm32f756xx pin and ball definition (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions lqfp100 wlcsp143 lqfp144 ufbga176 lqfp176 lqfp208 tfbga216
pinouts and pin description stm32f756xx 48/108 docid026379 rev 2 - - - e4 13 13 f3 pi11 i/o ft - otg_hs_ulpi_dir, eventout wkup4 - e7 - f2 14 14 f2 vss s - - - - -e10- f31515f4 vdd s - - - - - f11 10 e2 16 16 d2 pf0 i/o ft - i2c2_sda, fmc_a0, eventout - - e9 11 h3 17 17 e2 pf1 i/o ft - i2c2_scl, fmc_a1, eventout - - f10 12 h2 18 18 g2 pf2 i/o ft - i2c2_smba, fmc_a2, eventout - - - - - - 19 e3 pi12 i/o ft - lcd_hsync, eventout - - - - - - 20 g3 pi13 i/o ft - lcd_vsync, eventout - - - - - - 21 h3 pi14 i/o ft - lcd_clk, eventout - - g11 13 j2 19 22 h2 pf3 i/o ft - fmc_a3, eventout adc3_in9 - f9 14 j3 20 23 j2 pf4 i/o ft - fmc_a4, eventout adc3_in14 - f8 15 k3 21 24 k3 pf5 i/o ft - fmc_a5, eventout adc3_in15 10 h7 16 g2 22 25 h6 vss s - - - - 11 - 17 g3 23 26 h5 vdd s - - - - - g10 18 k2 24 27 k2 pf6 i/o ft - tim10_ch1, spi5_nss, sai1_sd_b, uart7_rx, quadspi_bk1_io3, eventout adc3_in4 - f7 19 k1 25 28 k1 pf7 i/o ft - tim11_ch1, spi5_sck, sai1_mclk_b, uart7_tx, quadspi_bk1_io2, eventout adc3_in5 table 10. stm32f756xx pin and ball definition (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions lqfp100 wlcsp143 lqfp144 ufbga176 lqfp176 lqfp208 tfbga216
docid026379 rev 2 49/108 stm32f756xx pinouts and pin description 80 - h11 20 l3 26 29 l3 pf8 i/o ft - spi5_miso, sai1_sck_b, uart7_rts, tim13_ch1, quadspi_bk1_io0, eventout adc3_in6 - g8 21 l2 27 30 l2 pf9 i/o ft - spi5_mosi, sai1_fs_b, uart7_cts, tim14_ch1, quadspi_bk1_io1, eventout adc3_in7 - g9 22 l1 28 31 l1 pf10 i/o ft - dcmi_d11, lcd_de, eventout adc3_in8 12 j11 23 g1 29 32 g1 ph0- osc_in( ph0) i/o ft - eventout osc_in (4) 13 h10 24 h1 30 33 h1 ph1- osc_ou t(ph1) i/o ft - eventout osc_out (4) 14 h9 25 j1 31 34 j1 nrst i/o rs t -- - 15 h8 26 m2 32 35 m2 pc0 i/o ft (4) sai2_fs_b, otg_hs_ulpi_stp, fmc_sdnwe, lcd_r5, eventout adc123_in10 16 k11 27 m3 33 36 m3 pc1 i/o ft (4) traced0, spi2_mosi/i2s2_sd, sai1_sd_a, eth_mdc, eventout adc123_in11, rtc_tamp3, wkup5 17 j10 28 m4 34 37 m4 pc2 i/o ft (4) spi2_miso, otg_hs_ulpi_dir, eth_mii_txd2, fmc_sdne0, eventout adc123_in12 table 10. stm32f756xx pin and ball definition (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions lqfp100 wlcsp143 lqfp144 ufbga176 lqfp176 lqfp208 tfbga216
pinouts and pin description stm32f756xx 50/108 docid026379 rev 2 18 j9 29 m5 35 38 l4 pc3 i/o ft (4) spi2_mosi/i2s2_sd, otg_hs_ulpi_nxt, eth_mii_tx_clk, fmc_sdcke0, eventout adc123_in13 -g730g33639j5 vdd s-- - - ------j6vsss-- - - 19 k10 31 m1 37 40 m1 vssa s - - - - ---n1--n1vref-s-- - - 20 l11 32 p1 38 41 p1 vref+ s - - - - 21 l10 33 r1 39 42 r1 vdda s - - - - 22 k9 34 n3 40 43 n3 pa0- wkup(p a0) i/o ft (5) tim2_ch1/tim2_etr, tim5_ch1, tim8_etr, usart2_cts, uart4_tx, sai2_sd_b, eth_mii_crs, eventout adc123_in0, wkup0 (4) 23 k8 35 n2 41 44 n2 pa1 i/o ft (4) tim2_ch2, tim5_ch2, usart2_rts, uart4_rx, quadspi_bk1_io3, sai2_mck_b, eth_mii_rx_clk/eth_ rmii_ref_clk, lcd_r2, eventout adc123_in1 24 l9 36 p2 42 45 p2 pa2 i/o ft (4) tim2_ch3, tim5_ch3, tim9_ch1, usart2_tx, sai2_sck_b, eth_mdio, lcd_r1, eventout adc123_in2, wkup1 - - - f4 43 46 k4 ph2 i/o ft lptim1_in2, quadspi_bk2_io0, sai2_sck_b, eth_mii_crs, fmc_sdcke0, lcd_r0, eventout - table 10. stm32f756xx pin and ball definition (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions lqfp100 wlcsp143 lqfp144 ufbga176 lqfp176 lqfp208 tfbga216
docid026379 rev 2 51/108 stm32f756xx pinouts and pin description 80 - - - g4 44 47 j4 ph3 i/o ft - quadspi_bk2_io1, sai2_mck_b, eth_mii_col, fmc_sdne0, lcd_r1, eventout - - - - h4 45 48 h4 ph4 i/o ft - i2c2_scl, otg_hs_ulpi_nxt, eventout - - - - j4 46 49 j3 ph5 i/o ft - i2c2_sda, spi5_nss, fmc_sdnwe, eventout - 25 m11 37 r2 47 50 r2 pa3 i/o ft (4) tim2_ch4, tim5_ch4, tim9_ch2, usart2_rx, otg_hs_ulpi_d0, eth_mii_col, lcd_b5, eventout adc123_in3 26 - 38 - - 51 k6 vss s - - - - -n11- l448 - l5 bypass _reg ift - - 27 j8 39 k4 49 52 k5 vdd s - - - - 28 m10 40 n4 50 53 n4 pa4 i/o tt a (4) spi1_nss/i2s1_ws, spi3_nss/i2s3_ws, usart2_ck, otg_hs_sof, dcmi_hsync, lcd_vsync, eventout adc12_in4, dac_out1 29 m9 41 p4 51 54 p4 pa5 i/o tt a (4) tim2_ch1/tim2_etr, tim8_ch1n, spi1_sck/i2s1_ck, otg_hs_ulpi_ck, lcd_r4, eventout adc12_in5, dac_out2 30 n10 42 p3 52 55 p3 pa6 i/o ft (4) tim1_bkin, tim3_ch1, tim8_bkin, spi1_miso, tim13_ch1, dcmi_pixclk, lcd_g2, eventout adc12_in6 table 10. stm32f756xx pin and ball definition (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions lqfp100 wlcsp143 lqfp144 ufbga176 lqfp176 lqfp208 tfbga216
pinouts and pin description stm32f756xx 52/108 docid026379 rev 2 31 l8 43 r3 53 56 r3 pa7 i/o ft (4) tim1_ch1n, tim3_ch2, tim8_ch1n, spi1_mosi/i2s1_sd, tim14_ch1, eth_mii_rx_dv/eth_r mii_crs_dv, fmc_sdnwe, eventout adc12_in7 32 m8 44 n5 54 57 n5 pc4 i/o ft (4) i2s1_mck, spdif_rx2, eth_mii_rxd0/eth_rm ii_rxd0, fmc_sdne0, eventout adc12_in14 33 n9 45 p5 55 58 p5 pc5 i/o ft (4) spdif_rx3, eth_mii_rxd1/eth_rm ii_rxd1, fmc_sdcke0, eventout adc12_in15 - j7 - - - 59 l7 vdd s - - - - -----60l6vsss-- - - 34 n8 46 r5 56 61 r5 pb0 i/o ft (4) tim1_ch2n, tim3_ch3, tim8_ch2n, uart4_cts, lcd_r3, otg_hs_ulpi_d1, eth_mii_rxd2, eventout adc12_in8 35 k7 47 r4 57 62 r4 pb1 i/o ft (4) tim1_ch3n, tim3_ch4, tim8_ch3n, lcd_r6, otg_hs_ulpi_d2, eth_mii_rxd3, eventout adc12_in9 36 l7 48 m6 58 63 m5 pb2 i/o ft - sai1_sd_a, spi3_mosi/i2s3_sd, quadspi_clk, eventout - - - - - - 64 g4 pi15 i/o ft - lcd_r0, eventout - - - - - - 65 r6 pj0 i/o ft - lcd_r1, eventout - - - - - - 66 r7 pj1 i/o ft - lcd_r2, eventout - - - - - - 67 p7 pj2 i/o ft - lcd_r3, eventout - table 10. stm32f756xx pin and ball definition (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions lqfp100 wlcsp143 lqfp144 ufbga176 lqfp176 lqfp208 tfbga216
docid026379 rev 2 53/108 stm32f756xx pinouts and pin description 80 - - - - - 68 n8 pj3 i/o ft - lcd_r4, eventout - - - - - - 69 m9 pj4 i/o ft - lcd_r5, eventout - - m749r65970p8 pf11 i/oft- spi5_mosi, sai2_sd_b, fmc_sdnras, dcmi_d12, eventout - - n7 50 p6 60 71 m6 pf12 i/o ft - fmc_a6, eventout - - - 51 m8 61 72 k7 vss s - - - - - - 52 n8 62 73 l8 vdd s - - - - - k6 53 n6 63 74 n6 pf13 i/o ft - i2c4_smba, fmc_a7, eventout - - l6 54 r7 64 75 p6 pf14 i/o ft - i2c4_scl, fmc_a8, eventout - - m655p76576m8 pf15 i/oft- i2c4_sda, fmc_a9, eventout - - n6 56 n7 66 77 n7 pg0 i/o ft - fmc_a10, eventout - - k5 57 m7 67 78 m7 pg1 i/o ft - fmc_a11, eventout - 37 l5 58 r8 68 79 r8 pe7 i/o ft - tim1_etr, uart7_rx, quadspi_bk2_io0, fmc_d4, eventout - 38 m5 59 p8 69 80 n9 pe8 i/o ft - tim1_ch1n, uart7_tx, quadspi_bk2_io1, fmc_d5, eventout - 39 n5 60 p9 70 81 p9 pe9 i/o ft - tim1_ch1, uart7_rts, quadspi_bk2_io2, fmc_d6, eventout - -h361m97182k8 vss s-- - - -j562n97283l9 vdd s-- - - 40 j4 63 r9 73 84 r9 pe10 i/o ft - tim1_ch2n, uart7_cts, quadspi_bk2_io3, fmc_d7, eventout - 41 k4 64 p10 74 85 p10 pe11 i/o ft - tim1_ch2, spi4_nss, sai2_sd_b, fmc_d8, lcd_g3, eventout - table 10. stm32f756xx pin and ball definition (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions lqfp100 wlcsp143 lqfp144 ufbga176 lqfp176 lqfp208 tfbga216
pinouts and pin description stm32f756xx 54/108 docid026379 rev 2 42 l4 65 r10 75 86 r10 pe12 i/o ft - tim1_ch3n, spi4_sck, sai2_sck_b, fmc_d9, lcd_b4, eventout - 43 n4 66 n11 76 87 r12 pe13 i/o ft - tim1_ch3, spi4_miso, sai2_fs_b, fmc_d10, lcd_de, eventout - 44 m4 67 p11 77 88 p11 pe14 i/o ft - tim1_ch4, spi4_mosi, sai2_mck_b, fmc_d11, lcd_clk, eventout - 45 l3 68 r11 78 89 r11 pe15 i/o ft - tim1_bkin, fmc_d12, lcd_r7, eventout - 46 m3 69 r12 79 90 p12 pb10 i/o ft - tim2_ch3, i2c2_scl, spi2_sck/i2s2_ck, usart3_tx, otg_hs_ulpi_d3, eth_mii_rx_er, lcd_g4, eventout - 47 n3 70 r13 80 91 r13 pb11 i/o ft - tim2_ch4, i2c2_sda, usart3_rx, otg_hs_ulpi_d4, eth_mii_tx_en/eth_r mii_tx_en, lcd_g5, eventout - 48 n2 71 m10 81 92 l11 vcap_1 s - - - - 49 h2 - - - 93 k9 vss s - - - - 50 j6 72 n10 82 94 l10 vdd s - - - - - - - - - 95 m14 pj5 i/o ft - lcd_r6, eventout - - - - m11 83 96 p13 ph6 i/o ft - i2c2_smba, spi5_sck, tim12_ch1, eth_mii_rxd2, fmc_sdne1, dcmi_d8, eventout - - - - n12 84 97 n13 ph7 i/o ft - i2c3_scl, spi5_miso, eth_mii_rxd3, fmc_sdcke1, dcmi_d9, eventout - table 10. stm32f756xx pin and ball definition (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions lqfp100 wlcsp143 lqfp144 ufbga176 lqfp176 lqfp208 tfbga216
docid026379 rev 2 55/108 stm32f756xx pinouts and pin description 80 - - - m12 85 98 p14 ph8 i/o ft - i2c3_sda, fmc_d16, dcmi_hsync, lcd_r2, eventout - - - - m13 86 99 n14 ph9 i/o ft - i2c3_smba, tim12_ch2, fmc_d17, dcmi_d0, lcd_r3, eventout - - - - l13 87 100 p15 ph10 i/o ft - tim5_ch1, i2c4_smba, fmc_d18, dcmi_d1, lcd_r4, eventout - - - - l12 88 101 n15 ph11 i/o ft - tim5_ch2, i2c4_scl, fmc_d19, dcmi_d2, lcd_r5, eventout - - - - k12 89 102 m15 ph12 i/o ft tim5_ch3, i2c4_sda, fmc_d20, dcmi_d3, lcd_r6, eventout - - - - h12 90 - k10 vss s - - - - - - - j12 91 103 k11 vdd s - - - - 51 m2 73 p12 92 104 l13 pb12 i/o ft - tim1_bkin, i2c2_smba, spi2_nss/i2s2_ws, usart3_ck, can2_rx, otg_hs_ulpi_d5, eth_mii_txd0/eth_rm ii_txd0, otg_hs_id, eventout - 52 n1 74 p13 93 105 k14 pb13 i/o ft - tim1_ch1n, spi2_sck/i2s2_ck, usart3_cts, can2_tx, otg_hs_ulpi_d6, eth_mii_txd1/eth_rm ii_txd1, eventout otg_hs_vbus table 10. stm32f756xx pin and ball definition (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions lqfp100 wlcsp143 lqfp144 ufbga176 lqfp176 lqfp208 tfbga216
pinouts and pin description stm32f756xx 56/108 docid026379 rev 2 53 k3 75 r14 94 106 r14 pb14 i/o ft - tim1_ch2n, tim8_ch2n, spi2_miso, usart3_rts, tim12_ch1, otg_hs_dm, eventout - 54 j3 76 r15 95 107 r15 pb15 i/o ft - rtc_refin, tim1_ch3n, tim8_ch3n, spi2_mosi/i2s2_sd, tim12_ch2, otg_hs_dp, eventout - 55 l2 77 p15 96 108 l15 pd8 i/o ft - usart3_tx, spdif_rx1, fmc_d13, eventout - 56 m1 78 p14 97 109 l14 pd9 i/o ft - usart3_rx, fmc_d14, eventout - 57 h4 79 n15 98 110 k15 pd10 i/o ft - usart3_ck, fmc_d15, lcd_b3, eventout - 58 k2 80 n14 99 111 n10 pd11 i/o ft - i2c4_smba, usart3_cts, quadspi_bk1_io0, sai2_sd_a, fmc_a16/fmc_cle, eventout - 59 h6 81 n13 100 112 m10 pd12 i/o ft - tim4_ch1, lptim1_in1, i2c4_scl, usart3_rts, quadspi_bk1_io1, sai2_fs_a, fmc_a17/fmc_ale, eventout - 60 h5 82 m15 101 113 m11 pd13 i/o ft - tim4_ch2, lptim1_out, i2c4_sda, quadspi_bk1_io3, sai2_sck_a, fmc_a18, eventout - table 10. stm32f756xx pin and ball definition (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions lqfp100 wlcsp143 lqfp144 ufbga176 lqfp176 lqfp208 tfbga216
docid026379 rev 2 57/108 stm32f756xx pinouts and pin description 80 - - 83 - 102 114 j10 vss s - - - - - l1 84 j13 103 115 j11 vdd s - - - - 61 j2 85 m14 104 116 l12 pd14 i/o ft - tim4_ch3, uart8_cts, fmc_d0, eventout - 62 k1 86 l14 105 117 k13 pd15 i/o ft - tim4_ch4, uart8_rts, fmc_d1, eventout - - - - - - 118 k12 pj6 i/o ft - lcd_r7, eventout - - - - - - 119 j12 pj7 i/o ft - lcd_g0, eventout - - - - - - 120 h12 pj8 i/o ft - lcd_g1, eventout - - - - - - 121 j13 pj9 i/o ft - lcd_g2, eventout - - - - - - 122 h13 pj10 i/o ft - lcd_g3, eventout - - - - - - 123 g12 pj11 i/o ft - lcd_g4, eventout - - - - - - 124 h11 vdd s - - - - -----125h10vsss-- - - - - - - - 126 g13 pk0 i/o ft - lcd_g5, eventout - - - - - - 127 f12 pk1 i/o ft - lcd_g6, eventout - - - - - - 128 f13 pk2 i/o ft - lcd_g7, eventout - - j1 87 l15 106 129 m13 pg2 i/o ft - fmc_a12, eventout - - g3 88 k15 107 130 m12 pg3 i/o ft - fmc_a13, eventout - - g5 89 k14 108 131 n12 pg4 i/o ft - fmc_a14/fmc_ba0, eventout - - g6 90 k13 109 132 n11 pg5 i/o ft - fmc_a15/fmc_ba1, eventout - - g4 91 j15 110 133 j15 pg6 i/o ft - dcmi_d12, lcd_r7, eventout - - h1 92 j14 111 134 j14 pg7 i/o ft - usart6_ck, fmc_int, dcmi_d13, lcd_clk, eventout - table 10. stm32f756xx pin and ball definition (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions lqfp100 wlcsp143 lqfp144 ufbga176 lqfp176 lqfp208 tfbga216
pinouts and pin description stm32f756xx 58/108 docid026379 rev 2 - g2 93 h14 112 135 h14 pg8 i/o ft - spi6_nss, spdif_rx2, usart6_rts, eth_pps_out, fmc_sdclk, eventout - - d2 94 g12 113 136 g10 vss s - - - - - g1 95 h13 114 137 g11 vddusb s - - - - 63 f2 96 h15 115 138 h15 pc6 i/o ft - tim3_ch1, tim8_ch1, i2s2_mck, usart6_tx, sdmmc_d6, dcmi_d0, lcd_hsync, eventout - 64 f3 97 g15 116 139 g15 pc7 i/o ft - tim3_ch2, tim8_ch2, i2s3_mck, usart6_rx, sdmmc_d7, dcmi_d1, lcd_g6, eventout - 65 e4 98 g14 117 140 g14 pc8 i/o ft - traced1, tim3_ch3, tim8_ch3, uart5_rts, usart6_ck, sdmmc_d0, dcmi_d2, eventout - 66 e3 99 f14 118 141 f14 pc9 i/o ft - mco2, tim3_ch4, tim8_ch4, i2c3_sda, i2s_ckin, uart5_cts, quadspi_bk1_io0, sdmmc_d1, dcmi_d3, eventout - 67 f1 100 f15 119 142 f15 pa8 i/o ft - mco1, tim1_ch1, tim8_bkin2, i2c3_scl, usart1_ck, otg_fs_sof, lcd_r6, eventout - 68 e2 101 e15 120 143 e15 pa9 i/o ft - tim1_ch2, i2c3_smba, spi2_sck/i2s2_ck, usart1_tx, dcmi_d0, eventout otg_fs_vbus table 10. stm32f756xx pin and ball definition (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions lqfp100 wlcsp143 lqfp144 ufbga176 lqfp176 lqfp208 tfbga216
docid026379 rev 2 59/108 stm32f756xx pinouts and pin description 80 69 d5 102 d15 121 144 d15 pa10 i/o ft - tim1_ch3, usart1_rx, otg_fs_id, dcmi_d1, eventout - 70 d4 103 c15 122 145 c15 pa11 i/o ft - tim1_ch4, usart1_cts, can1_rx, otg_fs_dm, lcd_r4, eventout - 71 e1 104 b15 123 146 b15 pa12 i/o ft - tim1_etr, usart1_rts, sai2_fs_b, can1_tx, otg_fs_dp, lcd_r5, eventout - 72 d3 105 a15 124 147 a15 pa13(jt ms- swdio) i/o ft - jtms-swdio, eventout - 73 d1 106 f13 125 148 e11 vcap_2 s - - - - 74 d2 107 f12 126 149 f10 vss s - - - - 75 c1 108 g13 127 150 f11 vdd s - - - - - - - e12 128 151 e12 ph13 i/o ft - tim8_ch1n, can1_tx, fmc_d21, lcd_g2, eventout - - - - e13 129 152 e13 ph14 i/o ft - tim8_ch2n, fmc_d22, dcmi_d4, lcd_g3, eventout - - - - d13 130 153 d13 ph15 i/o ft - tim8_ch3n, fmc_d23, dcmi_d11, lcd_g4, eventout - - - - e14 131 154 e14 pi0 i/o ft - tim5_ch4, spi2_nss/i2s2_ws, fmc_d24, dcmi_d13, lcd_g5, eventout - - - - d14 132 155 d14 pi1 i/o ft - tim8_bkin2, spi2_sck/i2s2_ck, fmc_d25, dcmi_d8, lcd_g6, eventout - table 10. stm32f756xx pin and ball definition (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions lqfp100 wlcsp143 lqfp144 ufbga176 lqfp176 lqfp208 tfbga216
pinouts and pin description stm32f756xx 60/108 docid026379 rev 2 - - - c14 133 156 c14 pi2 i/o ft - tim8_ch4, spi2_miso, fmc_d26, dcmi_d9, lcd_g7, eventout - - - - c13 134 157 c13 pi3 i/o ft - tim8_etr, spi2_mosi/i2s2_sd, fmc_d27, dcmi_d10, eventout - -f5-d9135-f9 vss s-- - - - a1 - c9 136 158 e10 vdd s - - - - 76 b1 109 a14 137 159 a14 pa14(jt ck- swclk) i/o ft - jtck-swclk, eventout - 77 c2 110 a13 138 160 a13 pa15(jt di) i/o ft - jtdi, tim2_ch1/tim2_etr, hdmi-cec, spi1_nss/i2s1_ws, spi3_nss/i2s3_ws, uart4_rts, eventout - 78 a2 111 b14 139 161 b14 pc10 i/o ft - spi3_sck/i2s3_ck, usart3_tx, uart4_tx, quadspi_bk1_io1, sdmmc_d2, dcmi_d8, lcd_r2, eventout - 79 b2 112 b13 140 162 b13 pc11 i/o ft - spi3_miso, usart3_rx, uart4_rx, quadspi_bk2_ncs, sdmmc_d3, dcmi_d4, eventout - 80 c3 113 a12 141 163 a12 pc12 i/o ft - traced3, spi3_mosi/i2s3_sd, usart3_ck, uart5_tx, sdmmc_ck, dcmi_d9, eventout - 81 b3 114 b12 142 164 b12 pd0 i/o ft - can1_rx, fmc_d2, eventout - table 10. stm32f756xx pin and ball definition (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions lqfp100 wlcsp143 lqfp144 ufbga176 lqfp176 lqfp208 tfbga216
docid026379 rev 2 61/108 stm32f756xx pinouts and pin description 80 82 c4 115 c12 143 165 c12 pd1 i/o ft - can1_tx, fmc_d3, eventout - 83 a3 116 d12 144 166 d12 pd2 i/o ft - traced2, tim3_etr, uart5_rx, sdmmc_cmd, dcmi_d11, eventout - 84 b4 117 d11 145 167 c11 pd3 i/o ft - spi2_sck/i2s2_ck, usart2_cts, fmc_clk, dcmi_d5, lcd_g7, eventout - 85 b5 118 d10 146 168 d11 pd4 i/o ft - usart2_rts, fmc_noe, eventout - 86 a4 119 c11 147 169 c10 pd5 i/o ft - usart2_tx, fmc_nwe, eventout - - - 120 d8 148 170 f8 vss s - - - - - c5 121 c8 149 171 e9 vdd s - - - - 87 f4 122 b11 150 172 b11 pd6 i/o ft - spi3_mosi/i2s3_sd, sai1_sd_a, usart2_rx, fmc_nwait, dcmi_d10, lcd_b2, eventout - 88 a5 123 a11 151 173 a11 pd7 i/o ft - usart2_ck, spdif_rx0, fmc_ne1, eventout - - - - - - 174 b10 pj12 i/o ft - lcd_b0, eventout - - - - - - 175 b9 pj13 i/o ft - lcd_b1, eventout - - - - - - 176 c9 pj14 i/o ft - lcd_b2, eventout - - - - - - 177 d10 pj15 i/o ft - lcd_b3, eventout - - e5 124 c10 152 178 d9 pg9 i/o ft - spdif_rx3, usart6_rx, quadspi_bk2_io2, sai2_fs_b, fmc_ne2/fmc_nce, dcmi_vsync, eventout - table 10. stm32f756xx pin and ball definition (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions lqfp100 wlcsp143 lqfp144 ufbga176 lqfp176 lqfp208 tfbga216
pinouts and pin description stm32f756xx 62/108 docid026379 rev 2 - c6 125 b10 153 179 c8 pg10 i/o ft - lcd_g3, sai2_sd_b, fmc_ne3, dcmi_d2, lcd_b2, eventout - - b6 126 b9 154 180 b8 pg11 i/o ft - spdif_rx0, eth_mii_tx_en/eth_r mii_tx_en, dcmi_d3, lcd_b3, eventout - - a6 127 b8 155 181 c7 pg12 i/o ft - lptim1_in1, spi6_miso, spdif_rx1, usart6_rts, lcd_b4, fmc_ne4, lcd_b1, eventout - - d6 128 a8 156 182 b3 pg13 i/o ft - traced0, lptim1_out, spi6_sck, usart6_cts, eth_mii_txd0/eth_rm ii_txd0, fmc_a24, lcd_r0, eventout - - f6 129 a7 157 183 a4 pg14 i/o ft - traced1, lptim1_etr, spi6_mosi, usart6_tx, quadspi_bk2_io3, eth_mii_txd1/eth_rm ii_txd1, fmc_a25, lcd_b0, eventout - - - 130 d7 158 184 f7 vss s - - - - - e6 131 c7 159 185 e8 vdd s - - - - - - - - - 186 d8 pk3 i/o ft - lcd_b4, eventout - - - - - - 187 d7 pk4 i/o ft - lcd_b5, eventout - - - - - - 188 c6 pk5 i/o ft - lcd_b6, eventout - - - - - - 189 c5 pk6 i/o ft - lcd_b7, eventout - - - - - - 190 c4 pk7 i/o ft - lcd_de, eventout - table 10. stm32f756xx pin and ball definition (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions lqfp100 wlcsp143 lqfp144 ufbga176 lqfp176 lqfp208 tfbga216
docid026379 rev 2 63/108 stm32f756xx pinouts and pin description 80 - a7 132 b7 160 191 b7 pg15 i/o ft - usart6_cts, fmc_sdncas, dcmi_d13, eventout - 89 b7 133 a10 161 192 a10 pb3(jtd o/trac eswo) i/o ft - jtdo/traceswo, tim2_ch2, spi1_sck/i2s1_ck, spi3_sck/i2s3_ck, eventout - 90 c7 134 a9 162 193 a9 pb4(njt rst) i/o ft - njtrst, tim3_ch1, spi1_miso, spi3_miso, spi2_nss/i2s2_ws, eventout - 91 c8 135 a6 163 194 a8 pb5 i/o ft - tim3_ch2, i2c1_smba, spi1_mosi/i2s1_sd, spi3_mosi/i2s3_sd, can2_rx, otg_hs_ulpi_d7, eth_pps_out, fmc_sdcke1, dcmi_d10, eventout - 92 a8 136 b6 164 195 b6 pb6 i/o ft - tim4_ch1, hdmi-cec, i2c1_scl, usart1_tx, can2_tx, quadspi_bk1_ncs, fmc_sdne1, dcmi_d5, eventout - 93 b8 137 b5 165 196 b5 pb7 i/o ft - tim4_ch2, i2c1_sda, usart1_rx, fmc_nl, dcmi_vsync, eventout - 94 c9 138 d6 166 197 e6 boot i b - - vpp 95 a9 139 a5 167 198 a7 pb8 i/o ft - tim4_ch3, tim10_ch1, i2c1_scl, can1_rx, eth_mii_txd3, sdmmc_d4, dcmi_d6, lcd_b6, eventout - table 10. stm32f756xx pin and ball definition (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions lqfp100 wlcsp143 lqfp144 ufbga176 lqfp176 lqfp208 tfbga216
pinouts and pin description stm32f756xx 64/108 docid026379 rev 2 96 b9 140 b4 168 199 b4 pb9 i/o ft - tim4_ch4, tim11_ch1, i2c1_sda, spi2_nss/i2s2_ws, can1_tx, sdmmc_d5, dcmi_d7, lcd_b7, eventout - 97 b10 141 a4 169 200 a6 pe0 i/o ft - tim4_etr, lptim1_etr, uart8_rx, sai2_mck_a, fmc_nbl0, dcmi_d2, eventout - 98 a10 142 a3 170 201 a5 pe1 i/o ft - lptim1_in2, uart8_tx, fmc_nbl1, dcmi_d3, eventout - 99 - - d5 - 202 f6 vss s - - - - - a11 143 c6 171 203 e5 pdr_on s - - - - 100 d7 144 c5 172 204 e7 vdd s - - - - - - - d4 173 205 c3 pi4 i/o ft - tim8_bkin, sai2_mck_a, fmc_nbl2, dcmi_d5, lcd_b4, eventout - - - - c4 174 206 d3 pi5 i/o ft - tim8_ch1, sai2_sck_a, fmc_nbl3, dcmi_vsync, lcd_b5, eventout - - - - c3 175 207 d6 pi6 i/o ft - tim8_ch2, sai2_sd_a, fmc_d28, dcmi_d6, lcd_b6, eventout - - - - c2 176 208 d4 pi7 i/o ft - tim8_ch3, sai2_fs_a, fmc_d29, dcmi_d7, lcd_b7, eventout - 1. function availability depends on the chosen device. table 10. stm32f756xx pin and ball definition (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions lqfp100 wlcsp143 lqfp144 ufbga176 lqfp176 lqfp208 tfbga216
docid026379 rev 2 65/108 stm32f756xx pinouts and pin description 80 2. pc13, pc14, pc15 and pi8 are supplied through the power swit ch. since the switch only sinks a limited amount of current (3 ma), the use of gpios pc13 to pc15 and pi8 in output mode is limited: - the speed should not exceed 2 mhz with a maximum load of 30 pf. - these i/os must not be used as a current source (e.g. to drive an led). 3. main function after the first backup domain power-up. later on, it depends on the contents of the rtc registers even after reset (because these registers are not reset by the main reset). for details on how to manage these i/os, refer to the rtc register description sections in the stm32f7xxx reference manual. 4. ft = 5 v tolerant except when in analog mode or oscillator mode (for pc14, pc15, ph0 and ph1). 5. if the device is delivered in an wlcsp143, ufbga176, lq fp176 or tfbga216 package, and the bypass_reg pin is set to v dd (regulator off/internal reset on mode), then pa0 is used as an internal reset (active low).
pinouts and pin description stm32f756xx 66/108 docid026379 rev 2 table 11. fmc pin definition pin name nor/psram/sr am nor/psram mux nand16 sdram pf0 a0 - - a0 pf1 a1 - - a1 pf2 a2 - - a2 pf3 a3 - - a3 pf4 a4 - - a4 pf5 a5 - - a5 pf12 a6 - - a6 pf13 a7 - - a7 pf14 a8 - - a8 pf15 a9 - - a9 pg0 a10 - - a10 pg1 a11 - - a11 pg2 a12 - - a12 pg3 a13 - - - pg4 a14 - - ba0 pg5 a15 - - ba1 pd11 a16 a16 cle - pd12 a17 a17 ale - pd13 a18 a18 - - pe3 a19 a19 - - pe4 a20 a20 - - pe5 a21 a21 - - pe6 a22 a22 - - pe2 a23 a23 - - pg13 a24 a24 - - pg14 a25 a25 - - pd14 d0 da0 d0 d0 pd15 d1 da1 d1 d1 pd0 d2 da2 d2 d2 pd1 d3 da3 d3 d3 pe7 d4 da4 d4 d4 pe8 d5 da5 d5 d5 pe9 d6 da6 d6 d6 pe10 d7 da7 d7 d7
docid026379 rev 2 67/108 stm32f756xx pinouts and pin description 80 pe11 d8 da8 d8 d8 pe12 d9 da9 d9 d9 pe13 d10 da10 d10 d10 pe14 d11 da11 d11 d11 pe15 d12 da12 d12 d12 pd8 d13 da13 d13 d13 pd9 d14 da14 d14 d14 pd10 d15 da15 d15 d15 ph8 d16 - - d16 ph9 d17 - - d17 ph10 d18 - - d18 ph11 d19 - - d19 ph12 d20 - - d20 ph13 d21 - - d21 ph14 d22 - - d22 ph15 d23 - - d23 pi0 d24 - - d24 pi1 d25 - - d25 pi2 d26 - - d26 pi3 d27 - - d27 pi6 d28 - - d28 pi7 d29 - - d29 pi9 d30 - - d30 pi10 d31 - - d31 pd7 ne1 ne1 - - pg9 ne2 ne2 nce - pg10 ne3 ne3 - - pg11---- pg12 ne4 ne4 - - pd3 clk clk - - pd4 noe noe noe - pd5 nwe nwe nwe - pd6 nwait nwait nwait - pb7 nadv nadv - - table 11. fmc pin definition (continued) pin name nor/psram/sr am nor/psram mux nand16 sdram
pinouts and pin description stm32f756xx 68/108 docid026379 rev 2 pf6 - - - - pf7 - - - - pf8 - - - - pf9 - - - - pf10---- pg6 - - - - pg7 - - int - pe0 nbl0 nbl0 - nbl0 pe1 nbl1 nbl1 - nbl1 pi4 nbl2 - - nbl2 pi5 nbl3 - - nbl3 pg8 - - - sdclk pc0 - - - sdnwe pf11 - - - sdnras pg15 - - - sdncas ph2 - - - sdcke0 ph3 - - - sdne0 ph6 - - - sdne1 ph7 - - - sdcke1 ph5 - - - sdnwe pc2 - - - sdne0 pc3 - - - sdcke0 pb5 - - - sdcke1 pb6 - - - sdne1 table 11. fmc pin definition (continued) pin name nor/psram/sr am nor/psram mux nand16 sdram
stm32f756xx pinouts and pin description docid026379 rev 2 69/108 table 12. stm32f756xx alternate function mapping port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/10/ 11/lptim 1/cec i2c1/2/3/ 4/cec spi1/2/3/ 4/5/6 spi3/ sai1 spi2/3/u sart1/2/ 3/uart5/ spdif sai2/us art6/ua rt4/5/7/8 /spdif can1/2/t im12/13/ 14/quad spi/lcd sai2/qu adspi/o tg2_hs/ otg1_fs eth/ otg1_fs fmc/sd mmc/ot g2_fs dcmi lcd sys port a pa0 - tim2_c h1/tim2 _etr tim5_c h1 tim8_et r --- usart2 _cts uart4_ tx - sai2_sd_ b eth_mii_ crs --- even tout pa1 - tim2_c h2 tim5_c h2 ---- usart2 _rts uart4_ rx quadsp i_bk1_io 3 sai2_mc k_b eth_mii_ rx_clk/ eth_rmi i_ref_c lk --lcd_r2 even tout pa2 - tim2_c h3 tim5_c h3 tim9_ch 1 --- usart2 _tx sai2_sc k_b -- eth_mdi o --lcd_r1 even tout pa3 - tim2_c h4 tim5_c h4 tim9_ch 2 --- usart2 _rx -- otg_hs_ ulpi_d0 eth_mii_ col - - lcd_b5 even tout pa4--- - - spi1_ns s/i2s1_ ws spi3_ns s/i2s3_ ws usart2 _ck -- - - otg_hs _sof dcmi_h sync lcd_vs ync even tout pa5 - tim2_c h1/tim2 _etr - tim8_ch 1n - spi1_sc k/i2s1_ ck ---- otg_hs_ ulpi_ck ---lcd_r4 even tout pa6 - tim1_b kin tim3_c h1 tim8_bki n - spi1_mi so -- - tim13_c h1 --- dcmi_pi xclk lcd_g2 even tout pa7 - tim1_c h1n tim3_c h2 tim8_ch 1n - spi1_m osi/i2s1 _sd -- - tim14_c h1 - eth_mii_ rx_dv/e th_rmii_ crs_dv fmc_sd nwe -- even tout pa8 mco1 tim1_c h1 - tim8_bki n2 i2c3_sc l -- usart1 _ck -- otg_fs_ sof ---lcd_r6 even tout pa9 - tim1_c h2 -- i2c3_sm ba spi2_sc k/i2s2_ ck - usart1 _tx -- - -- dcmi_d 0 - even tout pa10 - tim1_c h3 -- --- usart1 _rx -- otg_fs_ id -- dcmi_d 1 - even tout pa11 - tim1_c h4 -- --- usart1 _cts - can1_r x otg_fs_ dm ---lcd_r4 even tout pa12 - tim1_et r -- --- usart1 _rts sai2_fs _b can1_t x otg_fs_ dp ---lcd_r5 even tout
pinouts and pin description stm32f756xx 70/108 docid026379 rev 2 port a pa13 jtms- swdio -- - - -- - - - - - --- even tout pa14 jtck- swclk -- - - -- - - - - - --- even tout pa15 jtdi tim2_c h1/tim2 _etr -- hdmi- cec spi1_ns s/i2s1_ ws spi3_ns s/i2s3_ ws - uart4_ rts - - - --- even tout port b pb0 - tim1_c h2n tim3_c h3 tim8_ch 2n ---- uart4_ cts lcd_r3 otg_hs_ ulpi_d1 eth_mii_ rxd2 --- even tout pb1 - tim1_c h3n tim3_c h4 tim8_ch 3n - - - - - lcd_r6 otg_hs_ ulpi_d2 eth_mii_ rxd3 --- even tout pb2--- - - - sai1_sd _a spi3_mo si/i2s3_ sd quadsp i_clk - - --- even tout pb3 jtdo/t races wo tim2_c h2 -- - spi1_sc k/i2s1_ ck spi3_sc k/i2s3_ ck --- - ---- even tout pb4 njtrst - tim3_c h1 -- spi1_mi so spi3_mi so spi2_ns s/i2s2_ ws - - - - --- even tout pb5 - - tim3_c h2 - i2c1_sm ba spi1_m osi/i2s1 _sd spi3_m osi/i2s3 _sd -- can2_r x otg_hs_ ulpi_d7 eth_pps _out fmc_sd cke1 dcmi_d 10 - even tout pb6 - - tim4_c h1 hdmi- cec i2c1_sc l -- usart1 _tx - can2_t x quadspi _bk1_nc s - fmc_sd ne1 dcmi_d 5 - even tout pb7 - - tim4_c h2 - i2c1_sd a -- usart1 _rx - - - - fmc_nl dcmi_v sync - even tout pb8 - - tim4_c h3 tim10_c h1 i2c1_sc l -- - - can1_r x eth_mii_ txd3 sdmmc _d4 dcmi_d 6 lcd_b6 even tout pb9 - - tim4_c h4 tim11_ch 1 i2c1_sd a spi2_ns s/i2s2_ ws -- - can1_t x -- sdmmc _d5 dcmi_d 7 lcd_b7 even tout table 12. stm32f756xx alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/10/ 11/lptim 1/cec i2c1/2/3/ 4/cec spi1/2/3/ 4/5/6 spi3/ sai1 spi2/3/u sart1/2/ 3/uart5/ spdif sai2/us art6/ua rt4/5/7/8 /spdif can1/2/t im12/13/ 14/quad spi/lcd sai2/qu adspi/o tg2_hs/ otg1_fs eth/ otg1_fs fmc/sd mmc/ot g2_fs dcmi lcd sys
stm32f756xx pinouts and pin description docid026379 rev 2 71/108 port b pb10 - tim2_c h3 -- i2c2_sc l spi2_sc k/i2s2_ ck - usart3 _tx -- otg_hs_ ulpi_d3 eth_mii_ rx_er - - lcd_g4 even tout pb11 - tim2_c h4 -- i2c2_sd a -- usart3 _rx -- otg_hs_ ulpi_d4 eth_mii_ tx_en/e th_rmii_ tx_en - - lcd_g5 even tout pb12 - tim1_b kin -- i2c2_sm ba spi2_ns s/i2s2_ ws - usart3 _ck - can2_r x otg_hs_ ulpi_d5 eth_mii_ txd0/et h_rmii_t xd0 otg_hs _id -- even tout pb13 - tim1_c h1n -- - spi2_sc k/i2s2_ ck - usart3 _cts - can2_t x otg_hs_ ulpi_d6 eth_mii_ txd1/et h_rmii_t xd1 --- even tout pb14 - tim1_c h2n - tim8_ch 2n - spi2_mi so - usart3 _rts - tim12_c h1 -- otg_hs _dm -- even tout pb15 rtc_re fin tim1_c h3n - tim8_ch 3n - spi2_m osi/i2s2 _sd -- - tim12_c h2 -- otg_hs _dp -- even tout port c pc0--- - - -- - sai2_fs _b - otg_hs_ ulpi_st p - fmc_sd nwe -lcd_r5 even tout pc1 traced 0 -- - - spi2_m osi/i2s2 _sd sai1_sd _a --- - eth_md c --- even tout pc2--- - - spi2_mi so ---- otg_hs_ ulpi_dir eth_mii_ txd2 fmc_sd ne0 -- even tout pc3--- - - spi2_m osi/i2s2 _sd ---- otg_hs_ ulpi_nx t eth_mii_ tx_clk fmc_sd cke0 -- even tout pc4--- - - i2s1_m ck -- spdif_r x2 -- eth_mii_ rxd0/et h_rmii_ rxd0 fmc_sd ne0 -- even tout table 12. stm32f756xx alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/10/ 11/lptim 1/cec i2c1/2/3/ 4/cec spi1/2/3/ 4/5/6 spi3/ sai1 spi2/3/u sart1/2/ 3/uart5/ spdif sai2/us art6/ua rt4/5/7/8 /spdif can1/2/t im12/13/ 14/quad spi/lcd sai2/qu adspi/o tg2_hs/ otg1_fs eth/ otg1_fs fmc/sd mmc/ot g2_fs dcmi lcd sys
pinouts and pin description stm32f756xx 72/108 docid026379 rev 2 port c pc5--- - - -- - spdif_r x3 -- eth_mii_ rxd1/et h_rmii_ rxd1 fmc_sd cke0 -- even tout pc6 - - tim3_c h1 tim8_ch 1 - i2s2_m ck -- usart6 _tx --- sdmmc _d6 dcmi_d 0 lcd_hs ync even tout pc7 - - tim3_c h2 tim8_ ch2 -- i2s3_m ck - usart6 _rx --- sdmmc _d7 dcmi_d 1 lcd_g6 even tout pc8 traced 1 - tim3_c h3 tim8_ ch3 --- uart5_ rts usart6 _ck --- sdmmc _d0 dcmi_d 2 - even tout pc9 mco2 - tim3_c h4 tim8_ ch4 i2c3_sd a i2s_cki n - uart5_ cts - quadsp i_bk1_io 0 -- sdmmc _d1 dcmi_d 3 - even tout pc10--- - - - spi3_sc k/i2s3_ ck usart3 _tx uart4_t x quadsp i_bk1_io 1 -- sdmmc _d2 dcmi_d 8 lcd_r2 even tout pc11--- - - - spi3_mi so usart3 _rx uart4_ rx quadsp i_bk2_n cs -- sdmmc _d3 dcmi_d 4 - even tout pc12 traced 3 -- - - - spi3_m osi/i2s3 _sd usart3 _ck uart5_t x --- sdmmc _ck dcmi_d 9 - even tout pc13--- - - -- - - - - - --- even tout pc14--- - - -- - - - - - --- even tout pc15--- - - -- - - - - - --- even tout port d pd0--- - - -- - - can1_r x - - fmc_d2 - - even tout pd1--- - - -- - - can1_t x - - fmc_d3 - - even tout pd2 traced 2 - tim3_et r ----- uart5_ rx --- sdmmc _cmd dcmi_d 11 - even tout table 12. stm32f756xx alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/10/ 11/lptim 1/cec i2c1/2/3/ 4/cec spi1/2/3/ 4/5/6 spi3/ sai1 spi2/3/u sart1/2/ 3/uart5/ spdif sai2/us art6/ua rt4/5/7/8 /spdif can1/2/t im12/13/ 14/quad spi/lcd sai2/qu adspi/o tg2_hs/ otg1_fs eth/ otg1_fs fmc/sd mmc/ot g2_fs dcmi lcd sys
stm32f756xx pinouts and pin description docid026379 rev 2 73/108 port d pd3--- - - spi2_sc k/i2s2_ ck - usart2 _cts -- - - fmc_cl k dcmi_d 5 lcd_g7 even tout pd4--- - - -- usart2 _rts -- - - fmc_n oe -- even tout pd5--- - - -- usart2 _tx -- - - fmc_n we -- even tout pd6--- - - spi3_m osi/i2s3 _sd sai1_sd _a usart2 _rx -- - - fmc_n wait dcmi_d 10 lcd_b2 even tout pd7--- - - -- usart2 _ck spdif_r x0 --- fmc_ne 1 -- even tout pd8--- - - -- usart3 _tx spdif_r x1 --- fmc_d1 3 -- even tout pd9--- - - -- usart3 _rx -- - - fmc_d1 4 -- even tout pd10--- - - -- usart3 _ck -- - - fmc_d1 5 - lcd_b3 even tout pd11--- - i2c4_sm ba -- usart3 _cts - quadsp i_bk1_io 0 sai2_sd_ a - fmc_a1 6/fmc_ cle -- even tout pd12 - - tim4_c h1 lptim1_i n1 i2c4_sc l -- usart3 _rts - quadsp i_bk1_io 1 sai2_fs_ a - fmc_a1 7/fmc_ ale -- even tout pd13 - - tim4_c h2 lptim1_ out i2c4_sd a -- - - quadsp i_bk1_io 3 sai2_sc k_a - fmc_a1 8 -- even tout pd14 - - tim4_c h3 ----- uart8_ cts ---fmc_d0-- even tout pd15 - - tim4_c h4 ----- uart8_ rts ---fmc_d1-- even tout port e pe0 - - tim4_et r lptim1_e tr ---- uart8_ rx - sai2_mc k_a - fmc_nb l0 dcmi_d 2 - even tout table 12. stm32f756xx alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/10/ 11/lptim 1/cec i2c1/2/3/ 4/cec spi1/2/3/ 4/5/6 spi3/ sai1 spi2/3/u sart1/2/ 3/uart5/ spdif sai2/us art6/ua rt4/5/7/8 /spdif can1/2/t im12/13/ 14/quad spi/lcd sai2/qu adspi/o tg2_hs/ otg1_fs eth/ otg1_fs fmc/sd mmc/ot g2_fs dcmi lcd sys
pinouts and pin description stm32f756xx 74/108 docid026379 rev 2 port e pe1--- lptim1_i n2 ---- uart8_t x --- fmc_nb l1 dcmi_d 3 - even tout pe2 tracec lk -- - - spi4_sc k sai1_m clk_a -- quadsp i_bk1_io 2 - eth_mii_ txd3 fmc_a2 3 -- even tout pe3 traced 0 -- - - - sai1_sd _b --- - - fmc_a1 9 -- even tout pe4 traced 1 -- - - spi4_ns s sai1_fs _a --- - - fmc_a2 0 dcmi_d 4 lcd_b0 even tout pe5 traced 2 -- tim9_ch 1 - spi4_mi so sai1_sc k_a --- - - fmc_a2 1 dcmi_d 6 lcd_g0 even tout pe6 traced 3 tim1_b kin2 - tim9_ch 2 - spi4_m osi sai1_sd _a --- sai2_mc k_b - fmc_a2 2 dcmi_d 7 lcd_g1 even tout pe7 - tim1_et r -- ---- uart7_ rx - quadspi _bk2_io0 -fmc_d4- - even tout pe8 - tim1_c h1n -- ---- uart7_t x - quadspi _bk2_io1 -fmc_d5- - even tout pe9 - tim1_c h1 -- ---- uart7_ rts - quadspi _bk2_io2 -fmc_d6- - even tout pe10 - tim1_c h2n -- ---- uart7_ cts - quadspi _bk2_io3 -fmc_d7- - even tout pe11 - tim1_c h2 -- - spi4_ns s ---- sai2_sd_ b - fmc_d8 - lcd_g3 even tout pe12 - tim1_c h3n -- - spi4_sc k ---- sai2_sc k_b - fmc_d9 - lcd_b4 even tout pe13 - tim1_c h3 -- - spi4_mi so ---- sai2_fs_ b - fmc_d1 0 - lcd_de even tout pe14 - tim1_c h4 -- - spi4_m osi ---- sai2_mc k_b - fmc_d1 1 - lcd_cl k even tout pe15 - tim1_b kin -- ------ - - fmc_d1 2 -lcd_r7 even tout table 12. stm32f756xx alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/10/ 11/lptim 1/cec i2c1/2/3/ 4/cec spi1/2/3/ 4/5/6 spi3/ sai1 spi2/3/u sart1/2/ 3/uart5/ spdif sai2/us art6/ua rt4/5/7/8 /spdif can1/2/t im12/13/ 14/quad spi/lcd sai2/qu adspi/o tg2_hs/ otg1_fs eth/ otg1_fs fmc/sd mmc/ot g2_fs dcmi lcd sys
stm32f756xx pinouts and pin description docid026379 rev 2 75/108 port f pf0--- - i2c2_sd a -- - - - - -fmc_a0-- even tout pf1--- - i2c2_sc l -- - - - - -fmc_a1-- even tout pf2--- - i2c2_sm ba -- - - - - -fmc_a2-- even tout pf3--- - - -- - - - - -fmc_a3-- even tout pf4--- - - -- - - - - -fmc_a4-- even tout pf5--- - - -- - - - - -fmc_a5-- even tout pf6--- tim10_c h1 - spi5_ns s sai1_sd _b - uart7_ rx quadsp i_bk1_io 3 - - --- even tout pf7--- tim11_ch 1 - spi5_sc k sai1_m clk_b - uart7_t x quadsp i_bk1_io 2 - - --- even tout pf8--- - - spi5_mi so sai1_sc k_b - uart7_ rts tim13_c h1 quadspi _bk1_io0 - --- even tout pf9--- - - spi5_m osi sai1_fs _b - uart7_ cts tim14_c h1 quadspi _bk1_io1 - --- even tout pf10--- - - -- - - - - - - dcmi_d 11 lcd_de even tout pf11--- - - spi5_m osi ---- sai2_sd_ b - fmc_sd nras dcmi_d 12 - even tout pf12--- - - -- - - - - -fmc_a6-- even tout pf13--- - i2c4_sm ba -- - - - - -fmc_a7-- even tout pf14--- - i2c4_sc l -- - - - - -fmc_a8-- even tout pf15--- - i2c4_sd a -- - - - - -fmc_a9-- even tout table 12. stm32f756xx alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/10/ 11/lptim 1/cec i2c1/2/3/ 4/cec spi1/2/3/ 4/5/6 spi3/ sai1 spi2/3/u sart1/2/ 3/uart5/ spdif sai2/us art6/ua rt4/5/7/8 /spdif can1/2/t im12/13/ 14/quad spi/lcd sai2/qu adspi/o tg2_hs/ otg1_fs eth/ otg1_fs fmc/sd mmc/ot g2_fs dcmi lcd sys
pinouts and pin description stm32f756xx 76/108 docid026379 rev 2 port g pg0--- - - -- - - - - - fmc_a1 0 -- even tout pg1--- - - -- - - - - - fmc_a1 1 -- even tout pg2--- - - -- - - - - - fmc_a1 2 -- even tout pg3--- - - -- - - - - - fmc_a1 3 -- even tout pg4--- - - -- - - - - - fmc_a1 4/fmc_ ba0 -- even tout pg5--- - - -- - - - - - fmc_a1 5/fmc_ ba1 -- even tout pg6--- - - -- - - - - - - dcmi_d 12 lcd_r7 even tout pg7--- - - -- - usart6 _ck --- fmc_in t dcmi_d 13 lcd_cl k even tout pg8--- - - spi6_ns s - spdif_r x2 usart6 _rts -- eth_pps _out fmc_sd clk -- even tout pg9--- - - -- spdif_r x3 usart6 _rx quadsp i_bk2_io 2 sai2_fs_ b - fmc_ne 2/fmc_ nce dcmi_v sync - even tout pg10--- - - -- - -lcd_g3 sai2_sd_ b - fmc_ne 3 dcmi_d 2 lcd_b2 even tout pg11--- - - -- spdif_r x0 -- - eth_mii_ tx_en/e th_rmii_ tx_en - dcmi_d 3 lcd_b3 even tout pg12--- lptim1_i n1 - spi6_mi so - spdif_r x1 usart6 _rts lcd_b4 - - fmc_ne 4 - lcd_b1 even tout pg13 traced 0 -- lptim1_ out - spi6_sc k -- usart6 _cts -- eth_mii_ txd0/et h_rmii_t xd0 fmc_a2 4 -lcd_r0 even tout table 12. stm32f756xx alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/10/ 11/lptim 1/cec i2c1/2/3/ 4/cec spi1/2/3/ 4/5/6 spi3/ sai1 spi2/3/u sart1/2/ 3/uart5/ spdif sai2/us art6/ua rt4/5/7/8 /spdif can1/2/t im12/13/ 14/quad spi/lcd sai2/qu adspi/o tg2_hs/ otg1_fs eth/ otg1_fs fmc/sd mmc/ot g2_fs dcmi lcd sys
stm32f756xx pinouts and pin description docid026379 rev 2 77/108 port g pg14 traced 1 -- lptim1_e tr - spi6_m osi -- usart6 _tx quadsp i_bk2_io 3 - eth_mii_ txd1/et h_rmii_t xd1 fmc_a2 5 - lcd_b0 even tout pg15--- - - -- - usart6 _cts --- fmc_sd ncas dcmi_d 13 - even tout port h ph0--- - - -- - - - - - --- even tout ph1--- - - -- - - - - - --- even tout ph2--- lptim1_i n2 ----- quadsp i_bk2_io 0 sai2_sc k_b eth_mii_ crs fmc_sd cke0 -lcd_r0 even tout ph3--- - - -- - - quadsp i_bk2_io 1 sai2_mc k_b eth_mii_ col fmc_sd ne0 -lcd_r1 even tout ph4--- - i2c2_sc l ----- otg_hs_ ulpi_nx t - --- even tout ph5--- - i2c2_sd a spi5_ns s ---- - - fmc_sd nwe -- even tout ph6--- - i2c2_sm ba spi5_sc k -- - tim12_c h1 - eth_mii_ rxd2 fmc_sd ne1 dcmi_d 8 - even tout ph7--- - i2c3_sc l spi5_mi so ---- - eth_mii_ rxd3 fmc_sd cke1 dcmi_d 9 - even tout ph8--- - i2c3_sd a ----- - - fmc_d1 6 dcmi_h sync lcd_r2 even tout ph9--- - i2c3_sm ba -- - - tim12_c h2 -- fmc_d1 7 dcmi_d 0 lcd_r3 even tout ph10 - - tim5_c h1 - i2c4_sm ba ----- - - fmc_d1 8 dcmi_d 1 lcd_r4 even tout ph11 - - tim5_c h2 - i2c4_sc l ----- - - fmc_d1 9 dcmi_d 2 lcd_r5 even tout ph12 - - tim5_c h3 - i2c4_sd a ----- - - fmc_d2 0 dcmi_d 3 lcd_r6 even tout table 12. stm32f756xx alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/10/ 11/lptim 1/cec i2c1/2/3/ 4/cec spi1/2/3/ 4/5/6 spi3/ sai1 spi2/3/u sart1/2/ 3/uart5/ spdif sai2/us art6/ua rt4/5/7/8 /spdif can1/2/t im12/13/ 14/quad spi/lcd sai2/qu adspi/o tg2_hs/ otg1_fs eth/ otg1_fs fmc/sd mmc/ot g2_fs dcmi lcd sys
pinouts and pin description stm32f756xx 78/108 docid026379 rev 2 port h ph13--- tim8_ch 1n ----- can1_t x -- fmc_d2 1 - lcd_g2 even tout ph14--- tim8_ch 2n ------ - - fmc_d2 2 dcmi_d 4 lcd_g3 even tout ph15--- tim8_ch 3n ------ - - fmc_d2 3 dcmi_d 11 lcd_g4 even tout port i pi0 - - tim5_c h4 -- spi2_ns s/i2s2_ ws ---- - - fmc_d2 4 dcmi_d 13 lcd_g5 even tout pi1--- tim8_bki n2 - spi2_sc k/i2s2_ ck ---- - - fmc_d2 5 dcmi_d 8 lcd_g6 even tout pi2--- tim8_ch 4 - spi2_mi so ---- - - fmc_d2 6 dcmi_d 9 lcd_g7 even tout pi3--- tim8_et r - spi2_m osi/i2s2 _sd ---- - - fmc_d2 7 dcmi_d 10 - even tout pi4--- tim8_bki n ------ sai2_mc k_a - fmc_nb l2 dcmi_d 5 lcd_b4 even tout pi5--- tim8_ch 1 ------ sai2_sc k_a - fmc_nb l3 dcmi_v sync lcd_b5 even tout pi6--- tim8_ch 2 ------ sai2_sd_ a - fmc_d2 8 dcmi_d 6 lcd_b6 even tout pi7--- tim8_ch 3 ------ sai2_fs_ a - fmc_d2 9 dcmi_d 7 lcd_b7 even tout pi8--- - - -- - - - - - --- even tout pi9--- - - -- - - can1_r x -- fmc_d3 0 - lcd_vs ync even tout pi10--- - - -- - - - - eth_mii_ rx_er fmc_d3 1 - lcd_hs ync even tout pi11--- - - -- - - - otg_hs_ ulpi_dir - --- even tout table 12. stm32f756xx alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/10/ 11/lptim 1/cec i2c1/2/3/ 4/cec spi1/2/3/ 4/5/6 spi3/ sai1 spi2/3/u sart1/2/ 3/uart5/ spdif sai2/us art6/ua rt4/5/7/8 /spdif can1/2/t im12/13/ 14/quad spi/lcd sai2/qu adspi/o tg2_hs/ otg1_fs eth/ otg1_fs fmc/sd mmc/ot g2_fs dcmi lcd sys
stm32f756xx pinouts and pin description docid026379 rev 2 79/108 port i pi12--- - - -- - - - - - -- lcd_hs ync even tout pi13--- - - -- - - - - - -- lcd_vs ync even tout pi14--- - - -- - - - - - -- lcd_cl k even tout pi15--- - - -- - - - - - --lcd_r0 even tout port j pj0--- - - -- - - - - - --lcd_r1 even tout pj1--- - - -- - - - - - --lcd_r2 even tout pj2--- - - -- - - - - - --lcd_r3 even tout pj3--- - - -- - - - - - --lcd_r4 even tout pj4--- - - -- - - - - - --lcd_r5 even tout pj5--- - - -- - - - - - --lcd_r6 even tout pj6--- - - -- - - - - - --lcd_r7 even tout pj7--- - - -- - - - - - --lcd_g0 even tout pj8--- - - -- - - - - - --lcd_g1 even tout pj9--- - - -- - - - - - --lcd_g2 even tout pj10--- - - -- - - - - - --lcd_g3 even tout pj11--- - - -- - - - - - --lcd_g4 even tout table 12. stm32f756xx alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/10/ 11/lptim 1/cec i2c1/2/3/ 4/cec spi1/2/3/ 4/5/6 spi3/ sai1 spi2/3/u sart1/2/ 3/uart5/ spdif sai2/us art6/ua rt4/5/7/8 /spdif can1/2/t im12/13/ 14/quad spi/lcd sai2/qu adspi/o tg2_hs/ otg1_fs eth/ otg1_fs fmc/sd mmc/ot g2_fs dcmi lcd sys
pinouts and pin description stm32f756xx 80/108 docid026379 rev 2 port j pj12--- - - -- - - - - - --lcd_b0 even tout pj13--- - - -- - - - - - --lcd_b1 even tout pj14--- - - -- - - - - - --lcd_b2 even tout pj15--- - - -- - - - - - --lcd_b3 even tout port k pk0--- - - -- - - - - - --lcd_g5 even tout pk1--- - - -- - - - - - --lcd_g6 even tout pk2--- - - -- - - - - - --lcd_g7 even tout pk3--- - - -- - - - - - --lcd_b4 even tout pk4--- - - -- - - - - - --lcd_b5 even tout pk5--- - - -- - - - - - --lcd_b6 even tout pk6--- - - -- - - - - - --lcd_b7 even tout pk7--- - - -- - - - - - --lcd_de even tout table 12. stm32f756xx alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/10/ 11/lptim 1/cec i2c1/2/3/ 4/cec spi1/2/3/ 4/5/6 spi3/ sai1 spi2/3/u sart1/2/ 3/uart5/ spdif sai2/us art6/ua rt4/5/7/8 /spdif can1/2/t im12/13/ 14/quad spi/lcd sai2/qu adspi/o tg2_hs/ otg1_fs eth/ otg1_fs fmc/sd mmc/ot g2_fs dcmi lcd sys
docid026379 rev 2 81/108 stm32f756xx memory mapping 85 4 memory mapping the memory map is shown in figure 16 . figure 16. memory map 069 0e\wh %orfn &ruwh[0 ,qwhuqdo shulskhudov 0e\wh %orfn )0& 0e\wh %orfn 4xdg63,dqg )0&edqn [ [))))))) [ [))))))) [ [))))))) [ [))))))) [ [))))))) [& [&))))))) [' ['))))))) [( [)))))))) 65$0.% 5hvhuyhg [[)))) [[%))) [[))))))) [ 5hvhuyhg [))) [[)))) [ 5hvhuyhg [&[))))))) $+% [['))))))) $+% '7&0.% [%)) [ 65$0.% [&[)))) $3% $3% [%)) [&[)))) 5hvhuyhg [[))))))) [)))) $+% 5hvhuyhg )odvkphpru\rq$;,0lqwhuidfh [)))[)))) [[))))) [[)))))) [[))) 5hvhuyhg 2swlrq%\whv 5hvhuyhg [)))[))))))) [ &ruwh[0lqwhuqdo shulskhudov [([())))) 5hvhuyhg [([)))))))) 0e\wh %orfn )0& 0e\wh %orfn )0&edqnwr edqn 0e\wh %orfn 3hulskhudov 0e\wh %orfn 65$0 0e\wh %orfn 5hvhuyhg [[))()))) )odvkphpru\rq,7&0lqwhuidfh [[))))) [[))))) [[))))) ,7&05$0 5hvhuyhg 6\vwhpphpru\ 5hvhuyhg [[('%)
memory mapping stm32f756xx 82/108 docid026379 rev 2 table 13. stm32f756xx register boundary addresses bus boundary address peripheral 0xe00f ffff - 0xffff ffff reserved cortex-m7 0xe000 0000 - 0xe00f ffff cortex-m7 internal peripherals ahb3 0xd000 0000 - 0xdfff ffff fmc bank 6 0xc000 0000 - 0xcfff ffff fmc bank 5 0xa000 2000 - 0xbfff ffff reserved 0xa000 1000 - 0xa000 1fff quad spi control register 0xa000 0000- 0xa000 0fff fmc control register 0x9000 0000 - 0x9fff ffff quad spi 0x8000 0000 - 0x8fff ffff fmc bank 3 0x7000 0000 - 0x7fff ffff fmc bank 2 0x6000 0000 - 0x6fff ffff fmc bank 1 0x5006 0c00- 0x5fff ffff reserved ahb2 0x5006 0800 - 0x5006 0bff rng 0x5006 0400 - 0x5006 07ff hash 0x5006 0000 - 0x5006 03ff cryp 0x5005 0400 - 0x5006 07ff reserved 0x5005 0000 - 0x5005 03ff dcmi 0x5004 0000- 0x5004 ffff reserved 0x5000 0000 - 0x5003 ffff usb otg fs
docid026379 rev 2 83/108 stm32f756xx memory mapping 85 0x4008 0000- 0x4fff ffff reserved ahb1 0x4004 0000 - 0x4007 ffff usb otg hs 0x4002 bc00- 0x4003 ffff reserved 0x4002 b000 - 0x4002 bbff chrom-art (dma2d) 0x4002 9400 - 0x4002 afff reserved 0x4002 9000 - 0x4002 93ff ethernet mac 0x4002 8c00 - 0x4002 8fff 0x4002 8800 - 0x4002 8bff 0x4002 8400 - 0x4002 87ff 0x4002 8000 - 0x4002 83ff 0x4002 6800 - 0x4002 7fff reserved 0x4002 6400 - 0x4002 67ff dma2 0x4002 6000 - 0x4002 63ff dma1 0x4002 5000 - 0x4002 5fff reserved 0x4002 4000 - 0x4002 4fff bkpsram 0x4002 3c00 - 0x4002 3fff flash interface register 0x4002 3800 - 0x4002 3bff rcc 0x4002 3400 - 0x4002 37ff reserved 0x4002 3000 - 0x4002 33ff crc 0x4002 2c00 - 0x4002 2fff reserved 0x4002 2800 - 0x4002 2bff gpiok 0x4002 2400 - 0x4002 27ff gpioj 0x4002 2000 - 0x4002 23ff gpioi 0x4002 1c00 - 0x4002 1fff gpioh 0x4002 1800 - 0x4002 1bff gpiog 0x4002 1400 - 0x4002 17ff gpiof 0x4002 1000 - 0x4002 13ff gpioe 0x4002 0c00 - 0x4002 0fff gpiod 0x4002 0800 - 0x4002 0bff gpioc 0x4002 0400 - 0x4002 07ff gpiob 0x4002 0000 - 0x4002 03ff gpioa table 13. stm32f756xx register boundary addresses (continued) bus boundary address peripheral
memory mapping stm32f756xx 84/108 docid026379 rev 2 0x4001 6c00- 0x4001 ffff reserved apb2 0x4001 6800 - 0x4001 6bff lcd-tft 0x4001 6000 - 0x4001 67ff reserved 0x4001 5c00 - 0x4001 5fff sai2 0x4001 5800 - 0x4001 5bff sai1 0x4001 5400 - 0x4001 57ff spi6 0x4001 5000 - 0x4001 53ff spi5 0x4001 4c00 - 0x4001 4fff reserved 0x4001 4800 - 0x4001 4bff tim11 0x4001 4400 - 0x4001 47ff tim10 0x4001 4000 - 0x4001 43ff tim9 0x4001 3c00 - 0x4001 3fff exti 0x4001 3800 - 0x4001 3bff syscfg 0x4001 3400 - 0x4001 37ff spi4 0x4001 3000 - 0x4001 33ff spi1/i2s1 0x4001 2c00 - 0x4001 2fff sdmmc 0x4001 2400 - 0x4001 2bff reserved 0x4001 2000 - 0x4001 23ff adc1 - adc2 - adc3 0x4001 1800 - 0x4001 1fff reserved 0x4001 1400 - 0x4001 17ff usart6 0x4001 1000 - 0x4001 13ff usart1 0x4001 0800 - 0x4001 0fff reserved 0x4001 0400 - 0x4001 07ff tim8 0x4001 0000 - 0x4001 03ff tim1 table 13. stm32f756xx register boundary addresses (continued) bus boundary address peripheral
docid026379 rev 2 85/108 stm32f756xx memory mapping 85 0x4000 8000- 0x4000 ffff reserved apb1 0x4000 7c00 - 0x4000 7fff uart8 0x4000 7800 - 0x4000 7bff uart7 0x4000 7400 - 0x4000 77ff dac 0x4000 7000 - 0x4000 73ff pwr 0x4000 6c00 - 0x4000 6fff hdmi-cec 0x4000 6800 - 0x4000 6bff can2 0x4000 6400 - 0x4000 67ff can1 0x4000 6000 - 0x4000 63ff i2c4 0x4000 5c00 - 0x4000 5fff i2c3 0x4000 5800 - 0x4000 5bff i2c2 0x4000 5400 - 0x4000 57ff i2c1 0x4000 5000 - 0x4000 53ff uart5 0x4000 4c00 - 0x4000 4fff uart4 0x4000 4800 - 0x4000 4bff usart3 0x4000 4400 - 0x4000 47ff usart2 0x4000 4000 - 0x4000 43ff spdif-rx 0x4000 3c00 - 0x4000 3fff spi3 / i2s3 0x4000 3800 - 0x4000 3bff spi2 / i2s2 0x4000 3400 - 0x4000 37ff reserved 0x4000 3000 - 0x4000 33ff iwdg 0x4000 2c00 - 0x4000 2fff wwdg 0x4000 2800 - 0x4000 2bff rtc & bkp registers 0x4000 2400 - 0x4000 27ff lptim1 0x4000 2000 - 0x4000 23ff tim14 0x4000 1c00 - 0x4000 1fff tim13 0x4000 1800 - 0x4000 1bff tim12 0x4000 1400 - 0x4000 17ff tim7 0x4000 1000 - 0x4000 13ff tim6 0x4000 0c00 - 0x4000 0fff tim5 0x4000 0800 - 0x4000 0bff tim4 0x4000 0400 - 0x4000 07ff tim3 0x4000 0000 - 0x4000 03ff tim2 table 13. stm32f756xx register boundary addresses (continued) bus boundary address peripheral
package characteristics stm32f756xx 86/108 docid026379 rev 2 5 package characteristics 5.1 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. figure 17. lqfp100, 14 x 14 mm 100-pin low-profile quad flat package outline 1. drawing is not to scale. e )$%.4)&)#!4)/. 0). '!5'%0,!.% mm 3%!4).' 0,!.% $ $ $ % % % + ccc # # ,?-%?6 ! ! ! , , c b !
docid026379 rev 2 87/108 stm32f756xx package characteristics 107 table 14. lqpf100, 14 x 14 mm 100-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d 15.800 16.000 16.200 0.6220 0.6299 0.6378 d1 13.800 14.000 14.200 0.5433 0.5512 0.5591 d3 - 12.000 - - 0.4724 - e 15.800 16.000 16.200 0.6220 0.6299 0.6378 e1 13.800 14.000 14.200 0.5433 0.5512 0.5591 e3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 03.57 03.57 ccc - - 0.080 - - 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits.
package characteristics stm32f756xx 88/108 docid026379 rev 2 figure 18. lqpf100 re commended footprint 1. dimensions are expr essed in millimeters. device marking figure 19. lqfp100 marking example (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. ai 069 45.' 7(5 3 3urgxfwlghqwlilfdwlrq 5hylvlrqfrgh 88 : 'dwhfrgh 2swlrqdojdwhpdun 3lqlghqwlilhu
docid026379 rev 2 89/108 stm32f756xx package characteristics 107 figure 20. wlcsp143, 0.4 mm pitch wafe r level chip scale package outline 1. drawing is not to scale. !7% -%6 e & ' e e "ottomview "umpside e !balllocation &rontview ! ! $ !orientation reference 4opview 7aferbackside $etail! ! ! 3ideview ! % $etail! 2otated?# eee "ump 3eating plane b ! ! !
package characteristics stm32f756xx 90/108 docid026379 rev 2 table 15. wlcsp143, 0.4 mm pitch wafer level chip scale package mechanical data symbol millimeters inches (1) min typ max min typ max a 0.525 0.555 0.585 0.0207 0.0219 0.0230 a1 - 0.175 - - 0.0069 - a2 - 0.380 - - 0.0150 - a3 0.220 0.025 0.280 0.0087 0.0010 0.0110 b - 0.250 - - 0.250 - d 4.486 4.521 4.556 0.1766 0.1780 0.1794 e 5.512 5.547 5.582 0.2170 0.2184 0.2198 e - 0.400 - - 0.0157 - e1 - 4.000 - - 0.1575 - e2 - 4.800 - - 0.1890 - f - 0.261 - - 0.0103 - g - 0.374 - - 0.0147 - eee - 0.050 - - 0.0020 - 1. values in inches are converted from mm and rounded to 4 decimal digits.
docid026379 rev 2 91/108 stm32f756xx package characteristics 107 figure 21. lqfp144, 20 x 20 mm, 144-pin low-profile quad flat package outline 1. drawing is not to scale. e )$%.4)&)#!4)/. 0). '!5'%0,!.% mm 3%!4).' 0,!.% $ $ $ % % % + ccc # # !?-%?6 ! ! ! , , c b ! table 16. lqfp144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d 21.800 22.000 22.2 00 0.8583 0.8661 0.874 d1 19.800 20.000 20.200 0.7795 0.7874 0.7953 d3 - 17.500 - - 0.689 - e 21.800 22.000 22.200 0.8583 0.8661 0.8740
package characteristics stm32f756xx 92/108 docid026379 rev 2 figure 22. lqfp144 recommended footprint 1. dimensions are expr essed in millimeters. e1 19.800 20.000 20.200 0.7795 0.7874 0.7953 e3 - 17.500 - - 0.6890 - e - 0.500 - - 0.0197 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 03.57 03.57 ccc - - 0.080 - - 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. table 16. lqfp144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max aic
docid026379 rev 2 93/108 stm32f756xx package characteristics 107 device marking figure 23. lqfp144 marking example (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. -36 3lq lghqwlilhu 3 5hylvlrqfrgh ';(5 3urgxfwlghqwlilfdwlrq 'dwhfrgh :88 2swlrqdojdwhpdun
package characteristics stm32f756xx 94/108 docid026379 rev 2 figure 24. lqfp176 24 x 24 mm, 176-pin low-profile quad flat package outline 1. drawing is not to scale. 4?-%?6 ! ! e % (% $ ($ :$ :% b mm gaugeplane ! , , k c )$%.4)&)#!4)/. 0). 3eatingplane # ! table 17. lqfp176, 24 x 24 mm, 176-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 - 1.450 0.0531 - 0.0060 b 0.170 - 0.270 0.0067 - 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d 23.900 - 24.100 0.9409 - 0.9488 e 23.900 - 24.100 0.9409 - 0.9488 e - 0.500 - - 0.0197 - hd 25.900 - 26.100 1.0200 - 1.0276
docid026379 rev 2 95/108 stm32f756xx package characteristics 107 he 25.900 - 26.100 1.0200 - 1.0276 l 0.450 - 0.750 0.0177 - 0.0295 l1 - 1.000 - - 0.0394 - zd - 1.250 - - 0.0492 - ze - 1.250 - - 0.0492 - ccc - - 0.080 - - 0.0031 k 0 - 7 0 - 7 1. values in inches are converted from mm and rounded to 4 decimal digits. table 17. lqfp176, 24 x 24 mm, 176-pin low-profile quad flat package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max
package characteristics stm32f756xx 96/108 docid026379 rev 2 figure 25. lqfp176 recommended footprint 1. dimensions are expr essed in millimeters. 4?&0?6
docid026379 rev 2 97/108 stm32f756xx package characteristics 107 device marking figure 26. lqfp176 marking example (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 069 88 : 3lq lghqwlilhu 45.'*(5 3 'dwhfrgh 3urgxfwlghqwlilfdwlrq 5hylvlrqfrgh
package characteristics stm32f756xx 98/108 docid026379 rev 2 figure 27. lqfp208, 28 x 28 mm, 208-pi n low-profile quad flat package outline 1. drawing is not to scale. $ $ $ % % % e 0in identification !!! b c ! , , k 3eatingplane # ccc # mm gageplane 5(?-% table 18. lqfp208, 28 x 28 mm, 208-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.600 -- - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d 29.800 30.000 30.200 1.1732 1.1811 1.1890 d1 27.800 28.000 28.200 1.0945 1.1024 1.1102
docid026379 rev 2 99/108 stm32f756xx package characteristics 107 figure 28. lqfp208 recommended footprint 1. dimensions are expr essed in millimeters. d3 - 25.500 - - 1.0039 - e 29.800 30.000 30.200 1.1732 1.1811 1.1890 e1 27.800 28.000 28.200 1.0945 1.1024 1.1102 e3 - 25.500 - - 1.0039 - e - 0.500 - - 0.0197 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 0 3.5 7.0 0 3.5 7.0 ccc - - 0.080 - - 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. table 18. lqfp208, 28 x 28 mm, 208-pin low-profile quad flat package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max -36
package characteristics stm32f756xx 100/108 docid026379 rev 2 figure 29. ufbga176+25 - ultra thin fine pitch ball grid array 10 10 0.6 mm, package outline 1. drawing is not to scale. table 19. ufbga176+25 - ultra thin fine pitch ball grid array 10 10 0.6 mm mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 0.460 0.530 0.600 0.0181 0.0209 0.0236 a1 0.050 0.080 0.110 0.002 0.0031 0.0043 a2 0.400 0.450 0.500 0.0157 0.0177 0.0197 b 0.230 0.280 0.330 0.0091 0.0110 0.0130 d 9.950 10.000 10.050 0.3917 0.3937 0.3957 e 9.950 10.000 10.050 0.3917 0.3937 0.3957 e - 0.650 - - 0.0256 - f 0.400 0.450 0.500 0.0157 0.0177 0.0197 ddd - - 0.080 - - 0.0031 eee - - 0.150 - - 0.0059 fff - - 0.080 - - 0.0031 $(b0(b9 6hdwlqjsodqh $ & ggg $ $ h ) ) h 5 $ %277209,(: ( ' 7239,(: ?eedoov % $ % hhh ? 0 iii ? 0 & & $ & $edoo lghqwlilhu $edoo lqgh[duhd e
docid026379 rev 2 101/108 stm32f756xx package characteristics 107 device marking figure 30. ufbga176+25 marking example (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 069 5hylvlrqfrgh 670) 3urgxfwlghqwlilfdwlrq 'dwhfrgh <:: 3lq lqghqwlilhu ,*. 5
package characteristics stm32f756xx 102/108 docid026379 rev 2 figure 31. tfbga216 - thin fine pitch ball grid array 13 13 0.8mm, package outline 1. drawing is not to scale. $/b0(b9 6hdwlqjsodqh $ h ) ) ' 5 ?eedoov $ ( 7239,(: %277209,(: h $ $ < ; = ggg = ' ( hhh = < ; iii ? ? 0 0 = $edoo lghqwlilhu $edoo lqgh[duhd table 20. tfbga216 - thin fine pitc h ball grid array 13 13 0.8mm package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.100 - - 0.0433 a1 0.150 - - 0.0059 - - a2 - 0.760 - - 0.0299 - a4 - 0.210 - - 0.0083 - b 0.350 0.400 0.450 0.0138 0.0157 0.0177 d 12.850 13.000 13.150 0.5118 0.5118 0.5177 d1 - 11.200 - - 0.4409 - e 12.850 13.000 13.150 0.5118 0.5118 0.5177 e1 - 11.200 - - 0.4409 - e - 0.800 - - 0.0315 - f - 0.900 - - 0.0354 - ddd - - 0.080 - - 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits.
docid026379 rev 2 103/108 stm32f756xx package characteristics 107 device marking figure 32. tfbga216 marking example (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 069 %doo$ lghqwlilhu 'dwhfrgh :88 5hylvlrqfrgh 3urgxfwlghqwlilfdwlrq 3 45.' /()
package characteristics stm32f756xx 104/108 docid026379 rev 2 5.2 thermal characteristics the maximum chip-junction temperature, t j max, in degrees celsius, may be calculated using the following equation: t j max = t a max + (p d max x ja ) where: ? t a max is the maximum ambient temperature in c, ? ja is the package junction-to-ambient thermal resistance, in c/w, ? p d max is the sum of p int max and p i/o max (p d max = p int max + p i/o max), ? p int max is the product of i dd and v dd , expressed in watts. th is is the maximum chip internal power. p i/o max represents the maximum power dissipation on output pins where: p i/o max = (v ol i ol ) + ((v dd ? v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). available from www.jedec.org. table 21. package thermal characteristics symbol parameter value unit ja thermal resistance junction-ambient lqfp100 - 14 14 mm / 0.5 mm pitch 43 c/w thermal resistance junction-ambient wlcsp143 31.2 thermal resistance junction-ambient lqfp144 - 20 20 mm / 0.5 mm pitch 40 thermal resistance junction-ambient lqfp176 - 24 24 mm / 0.5 mm pitch 38 thermal resistance junction-ambient lqfp208 - 28 28 mm / 0.5 mm pitch 19 thermal resistance junction-ambient ufbga176 - 10 10 mm / 0.5 mm pitch 39 thermal resistance junction-ambient tfbga216 - 13 13 mm / 0.8 mm pitch 29
docid026379 rev 2 105/108 stm32f756xx part numbering 107 6 part numbering for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. table 22. ordering information scheme example: stm32 f 756 v g t 6 xxx device family stm32 = arm-based 32-bit microcontroller product type f = general-purpose device subfamily 756= stm32f756xx, usb otg fs/hs, camera interface, ethernet, lcd-tft, cryptographic acceleration pin count v = 100 pins z = 143 and 144 pins i = 176 pins b = 208 pins n = 216 pins flash memory size e = 512 kbytes of flash memory g = 1024 kbytes of flash memory package t = lqfp k = ufbga h = tfbga y = wlcsp temperature range 6 = industrial temperature range, ?40 to 85 c. 7 = industrial temperature range, ?40 to 105 c. options xxx = programmed parts tr = tape and reel
recommendations when using internal reset off stm32f756xx 106/108 docid026379 rev 2 appendix a recommendations wh en using internal reset off when the internal reset is off, the following integrated features are no longer supported: ? the integrated power-on reset (por) / power-down reset (pdr) circuitry is disabled. ? the brownout reset (bor) circuitry must be disabled. ? the embedded programmable voltage detector (pvd) is disabled. ? v bat functionality is no more available and vbat pin should be connected to v dd . ? the over-drive mode is not supported. a.1 operating conditions table 23. limitations depending on the operating power supply range operating power supply range adc operation maximum flash memory access frequency with no wait states (f flashmax ) maximum flash memory access frequency with wait states (1)(2) 1. applicable only when the code is executed from flash memory. wh en the code is executed from ram, no wait state is required. 2. thanks to the art accelerator and the 128-bit flash memory, the number of wait states given here does not impact the execution speed from flash memory since the art accelerator allows to achieve a performance equivalent to 0 wait state program execution. i/o operation possible flash memory operations v dd =1.7 to 2.1 v (3) 3. v dd /v dda minimum value of 1.7 v, with the use of an external power supply supervisor (refer to section 2.17.1: internal reset on ). conversion time up to 1.2 msps 20 mhz (4) 4. prefetch is not available. 168 mhz with 8 wait states and over-drive off ? no i/o compensation 8-bit erase and program operations only
docid026379 rev 2 107/108 stm32f756xx revision history 107 7 revision history table 24. document revision history date revision changes 09-sept-2014 1 initial release. 18-nov-2014 2 updated figure 1: compatible board design for lqfp100 package and figure 2: stm32f756xx block diagram . updated figure 16: memory map . updated figure 19: lqfp100 marking example (package top view) , figure 23: lqfp144 marking example (package top view) , figure 26: lqfp176 marking example (package top view) , figure 30: ufbga176+25 marking example (package top view) and figure 32: tfbga216 marking example (package top view) .
stm32f756xx 108/108 docid026379 rev 2 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics ? all rights reserved

▲Up To Search▲

Price & Availability of STM32F756NG

	To Download STM32F756NG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .